diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1193-drm-amdgpu-update-UMC-6.1-RAS-error-counter-register.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1193-drm-amdgpu-update-UMC-6.1-RAS-error-counter-register.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1193-drm-amdgpu-update-UMC-6.1-RAS-error-counter-register.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1193-drm-amdgpu-update-UMC-6.1-RAS-error-counter-register.patch new file mode 100644 index 00000000..590e892b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1193-drm-amdgpu-update-UMC-6.1-RAS-error-counter-register.patch @@ -0,0 +1,64 @@ +From 0b2d32f8241cc21851f3dcaf7a3bad34207317a0 Mon Sep 17 00:00:00 2001 +From: John Clements <john.clements@amd.com> +Date: Thu, 2 Jan 2020 11:32:15 +0800 +Subject: [PATCH 1193/1453] drm/amdgpu: update UMC 6.1 RAS error counter + register access path + +use proper method for SMN register access + +Change-Id: I5745d08cf5b616b81fa9427fc4c056d3f4957103 +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +Signed-off-by: John Clements <john.clements@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +index 5093965dbc24..23178399667c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +@@ -139,7 +139,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, + + /* check for SRAM correctable error + MCUMC_STATUS is a 64 bit register */ +- mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); ++ mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); + if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) +@@ -164,7 +164,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev + } + + /* check the MCUMC_STATUS */ +- mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); ++ mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); + if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && + (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || +@@ -211,12 +211,12 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, + /* skip error address process if -ENOMEM */ + if (!err_data->err_addr) { + /* clear umc status */ +- WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); ++ WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); + return; + } + + err_rec = &err_data->err_addr[err_data->err_addr_cnt]; +- mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); ++ mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); + + /* calculate error address if ue/ce error is detected */ + if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && +@@ -251,7 +251,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, + } + + /* clear umc status */ +- WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); ++ WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); + } + + static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, +-- +2.17.1 + |