diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0545-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0545-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0545-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0545-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch new file mode 100644 index 00000000..ba42c2c0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0545-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch @@ -0,0 +1,63 @@ +From 54c954adeca1e897c4416a75200c241f5bf77ba9 Mon Sep 17 00:00:00 2001 +From: Michael Strauss <michael.strauss@amd.com> +Date: Tue, 1 Oct 2019 11:24:32 -0400 +Subject: [PATCH 0545/1453] drm/amd/display: Fix MPO & pipe split on 3-pipe + dcn2x + +[WHY] +DML is incorrectly initialized with 4 pipes on 3 pipe configs +RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe +case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display) + +[HOW] +Set correct number of DPP/OTGs for dml init to generate correct DPP topology +Double RequiredDPPCLK after clock is halved for pipe split +and find_secondary_pipe fails to fix underflow + +Signed-off-by: Michael Strauss <michael.strauss@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++-- + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 ++++++++ + 2 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 6713a7cfedf0..3f23dbce2356 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2487,9 +2487,10 @@ bool dcn20_fast_validate_bw( + /* pipe not split previously needs split */ + hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); + ASSERT(hsplit_pipe); +- if (!hsplit_pipe) ++ if (!hsplit_pipe) { ++ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; + continue; +- ++ } + if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { + if (!dcn20_split_stream_for_odm( + &context->res_ctx, dc->res_pool, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index d2e851e7a97f..5e3b48bb04f1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -1722,6 +1722,14 @@ static bool construct( + + pool->base.pp_smu = dcn21_pp_smu_create(ctx); + ++ uint32_t num_pipes = dcn2_1_ip.max_num_dpp; ++ ++ for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) ++ if (pipe_fuses & 1 << i) ++ num_pipes--; ++ dcn2_1_ip.max_num_dpp = num_pipes; ++ dcn2_1_ip.max_num_otg = num_pipes; ++ + dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); + + init_data.ctx = dc->ctx; +-- +2.17.1 + |