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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0008-x86-cpu-Rename-cpu_data.x86_mask-to-cpu_data.x86_ste.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.9.21/0008-x86-cpu-Rename-cpu_data.x86_mask-to-cpu_data.x86_ste.patch760
1 files changed, 0 insertions, 760 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0008-x86-cpu-Rename-cpu_data.x86_mask-to-cpu_data.x86_ste.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0008-x86-cpu-Rename-cpu_data.x86_mask-to-cpu_data.x86_ste.patch
deleted file mode 100644
index 5dc0b927..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0008-x86-cpu-Rename-cpu_data.x86_mask-to-cpu_data.x86_ste.patch
+++ /dev/null
@@ -1,760 +0,0 @@
-From 4ac936f6e6b191d2eac4083da651826a8bb7b03b Mon Sep 17 00:00:00 2001
-From: Jia Zhang <qianyue.zj@alibaba-inc.com>
-Date: Mon, 1 Jan 2018 09:52:10 +0800
-Subject: [PATCH 08/12] x86/cpu: Rename cpu_data.x86_mask to
- cpu_data.x86_stepping
-
-commit b399151cb48db30ad1e0e93dd40d68c6d007b637 upstream.
-
-x86_mask is a confusing name which is hard to associate with the
-processor's stepping.
-
-Additionally, correct an indent issue in lib/cpu.c.
-
-Signed-off-by: Jia Zhang <qianyue.zj@alibaba-inc.com>
-[ Updated it to more recent kernels. ]
-Cc: Linus Torvalds <torvalds@linux-foundation.org>
-Cc: Peter Zijlstra <peterz@infradead.org>
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Cc: bp@alien8.de
-Cc: tony.luck@intel.com
-Link: http://lkml.kernel.org/r/1514771530-70829-1-git-send-email-qianyue.zj@alibaba-inc.com
-Signed-off-by: Ingo Molnar <mingo@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/events/intel/core.c | 2 +-
- arch/x86/events/intel/lbr.c | 2 +-
- arch/x86/events/intel/p6.c | 2 +-
- arch/x86/include/asm/acpi.h | 2 +-
- arch/x86/include/asm/processor.h | 2 +-
- arch/x86/kernel/amd_nb.c | 2 +-
- arch/x86/kernel/asm-offsets_32.c | 2 +-
- arch/x86/kernel/cpu/amd.c | 26 +++++++++++++-------------
- arch/x86/kernel/cpu/centaur.c | 4 ++--
- arch/x86/kernel/cpu/common.c | 8 ++++----
- arch/x86/kernel/cpu/cyrix.c | 2 +-
- arch/x86/kernel/cpu/intel.c | 18 +++++++++---------
- arch/x86/kernel/cpu/microcode/intel.c | 2 +-
- arch/x86/kernel/cpu/mtrr/generic.c | 2 +-
- arch/x86/kernel/cpu/mtrr/main.c | 4 ++--
- arch/x86/kernel/cpu/proc.c | 4 ++--
- arch/x86/kernel/head_32.S | 4 ++--
- arch/x86/kernel/mpparse.c | 2 +-
- arch/x86/lib/cpu.c | 2 +-
- drivers/char/hw_random/via-rng.c | 2 +-
- drivers/cpufreq/acpi-cpufreq.c | 2 +-
- drivers/cpufreq/longhaul.c | 6 +++---
- drivers/cpufreq/p4-clockmod.c | 2 +-
- drivers/cpufreq/powernow-k7.c | 2 +-
- drivers/cpufreq/speedstep-centrino.c | 4 ++--
- drivers/cpufreq/speedstep-lib.c | 6 +++---
- drivers/crypto/padlock-aes.c | 2 +-
- drivers/edac/amd64_edac.c | 2 +-
- drivers/edac/mce_amd.c | 2 +-
- drivers/hwmon/coretemp.c | 6 +++---
- drivers/hwmon/hwmon-vid.c | 2 +-
- drivers/hwmon/k10temp.c | 2 +-
- drivers/hwmon/k8temp.c | 2 +-
- drivers/video/fbdev/geode/video_gx.c | 2 +-
- 34 files changed, 68 insertions(+), 68 deletions(-)
-
-diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
-index cb85222..6b251fcc 100644
---- a/arch/x86/events/intel/core.c
-+++ b/arch/x86/events/intel/core.c
-@@ -3360,7 +3360,7 @@ static int intel_snb_pebs_broken(int cpu)
- break;
-
- case INTEL_FAM6_SANDYBRIDGE_X:
-- switch (cpu_data(cpu).x86_mask) {
-+ switch (cpu_data(cpu).x86_stepping) {
- case 6: rev = 0x618; break;
- case 7: rev = 0x70c; break;
- }
-diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
-index 81b321a..34ba350 100644
---- a/arch/x86/events/intel/lbr.c
-+++ b/arch/x86/events/intel/lbr.c
-@@ -1128,7 +1128,7 @@ void __init intel_pmu_lbr_init_atom(void)
- * on PMU interrupt
- */
- if (boot_cpu_data.x86_model == 28
-- && boot_cpu_data.x86_mask < 10) {
-+ && boot_cpu_data.x86_stepping < 10) {
- pr_cont("LBR disabled due to erratum");
- return;
- }
-diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
-index 1f5c47a..c5e441b 100644
---- a/arch/x86/events/intel/p6.c
-+++ b/arch/x86/events/intel/p6.c
-@@ -233,7 +233,7 @@ static __initconst const struct x86_pmu p6_pmu = {
-
- static __init void p6_pmu_rdpmc_quirk(void)
- {
-- if (boot_cpu_data.x86_mask < 9) {
-+ if (boot_cpu_data.x86_stepping < 9) {
- /*
- * PPro erratum 26; fixed in stepping 9 and above.
- */
-diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
-index 5391b0a..d32bab6 100644
---- a/arch/x86/include/asm/acpi.h
-+++ b/arch/x86/include/asm/acpi.h
-@@ -92,7 +92,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
- if (boot_cpu_data.x86 == 0x0F &&
- boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
- boot_cpu_data.x86_model <= 0x05 &&
-- boot_cpu_data.x86_mask < 0x0A)
-+ boot_cpu_data.x86_stepping < 0x0A)
- return 1;
- else if (amd_e400_c1e_detected)
- return 1;
-diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
-index a781668..df29212 100644
---- a/arch/x86/include/asm/processor.h
-+++ b/arch/x86/include/asm/processor.h
-@@ -88,7 +88,7 @@ struct cpuinfo_x86 {
- __u8 x86; /* CPU family */
- __u8 x86_vendor; /* CPU vendor */
- __u8 x86_model;
-- __u8 x86_mask;
-+ __u8 x86_stepping;
- #ifdef CONFIG_X86_32
- char wp_works_ok; /* It doesn't on 386's */
-
-diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
-index 458da85..8fe41c6 100644
---- a/arch/x86/kernel/amd_nb.c
-+++ b/arch/x86/kernel/amd_nb.c
-@@ -231,7 +231,7 @@ int amd_cache_northbridges(void)
- if (boot_cpu_data.x86 == 0x10 &&
- boot_cpu_data.x86_model >= 0x8 &&
- (boot_cpu_data.x86_model > 0x9 ||
-- boot_cpu_data.x86_mask >= 0x1))
-+ boot_cpu_data.x86_stepping >= 0x1))
- amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
-
- if (boot_cpu_data.x86 == 0x15)
-diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
-index 880aa09..36ebb6d 100644
---- a/arch/x86/kernel/asm-offsets_32.c
-+++ b/arch/x86/kernel/asm-offsets_32.c
-@@ -20,7 +20,7 @@ void foo(void)
- OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
- OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
- OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
-- OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
-+ OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
- OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
- OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
- OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
-diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
-index 1b89f0c..c375bc6 100644
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -118,7 +118,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
- return;
- }
-
-- if (c->x86_model == 6 && c->x86_mask == 1) {
-+ if (c->x86_model == 6 && c->x86_stepping == 1) {
- const int K6_BUG_LOOP = 1000000;
- int n;
- void (*f_vide)(void);
-@@ -147,7 +147,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
-
- /* K6 with old style WHCR */
- if (c->x86_model < 8 ||
-- (c->x86_model == 8 && c->x86_mask < 8)) {
-+ (c->x86_model == 8 && c->x86_stepping < 8)) {
- /* We can only write allocate on the low 508Mb */
- if (mbytes > 508)
- mbytes = 508;
-@@ -166,7 +166,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
- return;
- }
-
-- if ((c->x86_model == 8 && c->x86_mask > 7) ||
-+ if ((c->x86_model == 8 && c->x86_stepping > 7) ||
- c->x86_model == 9 || c->x86_model == 13) {
- /* The more serious chips .. */
-
-@@ -219,7 +219,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
- * As per AMD technical note 27212 0.2
- */
-- if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
-+ if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
- rdmsr(MSR_K7_CLK_CTL, l, h);
- if ((l & 0xfff00000) != 0x20000000) {
- pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
-@@ -239,12 +239,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- * but they are not certified as MP capable.
- */
- /* Athlon 660/661 is valid. */
-- if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
-- (c->x86_mask == 1)))
-+ if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
-+ (c->x86_stepping == 1)))
- return;
-
- /* Duron 670 is valid */
-- if ((c->x86_model == 7) && (c->x86_mask == 0))
-+ if ((c->x86_model == 7) && (c->x86_stepping == 0))
- return;
-
- /*
-@@ -254,8 +254,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
- * more.
- */
-- if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
-- ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
-+ if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
-+ ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
- (c->x86_model > 7))
- if (cpu_has(c, X86_FEATURE_MP))
- return;
-@@ -569,7 +569,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
- /* Set MTRR capability flag if appropriate */
- if (c->x86 == 5)
- if (c->x86_model == 13 || c->x86_model == 9 ||
-- (c->x86_model == 8 && c->x86_mask >= 8))
-+ (c->x86_model == 8 && c->x86_stepping >= 8))
- set_cpu_cap(c, X86_FEATURE_K6_MTRR);
- #endif
- #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
-@@ -834,11 +834,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
- /* AMD errata T13 (order #21922) */
- if ((c->x86 == 6)) {
- /* Duron Rev A0 */
-- if (c->x86_model == 3 && c->x86_mask == 0)
-+ if (c->x86_model == 3 && c->x86_stepping == 0)
- size = 64;
- /* Tbird rev A1/A2 */
- if (c->x86_model == 4 &&
-- (c->x86_mask == 0 || c->x86_mask == 1))
-+ (c->x86_stepping == 0 || c->x86_stepping == 1))
- size = 256;
- }
- return size;
-@@ -975,7 +975,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- }
-
- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_mask;
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
- while ((range = *erratum++))
- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
- (ms >= AMD_MODEL_RANGE_START(range)) &&
-diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
-index 1661d8e..4d2f61f 100644
---- a/arch/x86/kernel/cpu/centaur.c
-+++ b/arch/x86/kernel/cpu/centaur.c
-@@ -134,7 +134,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
- clear_cpu_cap(c, X86_FEATURE_TSC);
- break;
- case 8:
-- switch (c->x86_mask) {
-+ switch (c->x86_stepping) {
- default:
- name = "2";
- break;
-@@ -209,7 +209,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
- * - Note, it seems this may only be in engineering samples.
- */
- if ((c->x86 == 6) && (c->x86_model == 9) &&
-- (c->x86_mask == 1) && (size == 65))
-+ (c->x86_stepping == 1) && (size == 65))
- size -= 1;
- return size;
- }
-diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
-index 08e89ed..96b2c83 100644
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -699,7 +699,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
- cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
- c->x86 = x86_family(tfms);
- c->x86_model = x86_model(tfms);
-- c->x86_mask = x86_stepping(tfms);
-+ c->x86_stepping = x86_stepping(tfms);
-
- if (cap0 & (1<<19)) {
- c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
-@@ -1146,7 +1146,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
- c->loops_per_jiffy = loops_per_jiffy;
- c->x86_cache_size = -1;
- c->x86_vendor = X86_VENDOR_UNKNOWN;
-- c->x86_model = c->x86_mask = 0; /* So far unknown... */
-+ c->x86_model = c->x86_stepping = 0; /* So far unknown... */
- c->x86_vendor_id[0] = '\0'; /* Unset */
- c->x86_model_id[0] = '\0'; /* Unset */
- c->x86_max_cores = 1;
-@@ -1391,8 +1391,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
-
- pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
-
-- if (c->x86_mask || c->cpuid_level >= 0)
-- pr_cont(", stepping: 0x%x)\n", c->x86_mask);
-+ if (c->x86_stepping || c->cpuid_level >= 0)
-+ pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
- else
- pr_cont(")\n");
-
-diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
-index bd9dcd6..455d8ad 100644
---- a/arch/x86/kernel/cpu/cyrix.c
-+++ b/arch/x86/kernel/cpu/cyrix.c
-@@ -212,7 +212,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
-
- /* common case step number/rev -- exceptions handled below */
- c->x86_model = (dir1 >> 4) + 1;
-- c->x86_mask = dir1 & 0xf;
-+ c->x86_stepping = dir1 & 0xf;
-
- /* Now cook; the original recipe is by Channing Corn, from Cyrix.
- * We do the same thing for each generation: we work out
-diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
-index 02cb2e3..6ed206b 100644
---- a/arch/x86/kernel/cpu/intel.c
-+++ b/arch/x86/kernel/cpu/intel.c
-@@ -105,7 +105,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
-
- for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
- if (c->x86_model == spectre_bad_microcodes[i].model &&
-- c->x86_mask == spectre_bad_microcodes[i].stepping)
-+ c->x86_stepping == spectre_bad_microcodes[i].stepping)
- return (c->microcode <= spectre_bad_microcodes[i].microcode);
- }
- return false;
-@@ -158,7 +158,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
- * need the microcode to have already been loaded... so if it is
- * not, recommend a BIOS update and disable large pages.
- */
-- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
-+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
- c->microcode < 0x20e) {
- pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
-@@ -174,7 +174,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
-
- /* CPUID workaround for 0F33/0F34 CPU */
- if (c->x86 == 0xF && c->x86_model == 0x3
-- && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
-+ && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
- c->x86_phys_bits = 36;
-
- /*
-@@ -289,7 +289,7 @@ int ppro_with_ram_bug(void)
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- boot_cpu_data.x86 == 6 &&
- boot_cpu_data.x86_model == 1 &&
-- boot_cpu_data.x86_mask < 8) {
-+ boot_cpu_data.x86_stepping < 8) {
- pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
- return 1;
- }
-@@ -306,7 +306,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
- * Mask B, Pentium, but not Pentium MMX
- */
- if (c->x86 == 5 &&
-- c->x86_mask >= 1 && c->x86_mask <= 4 &&
-+ c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
- c->x86_model <= 3) {
- /*
- * Remember we have B step Pentia with bugs
-@@ -349,7 +349,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
- * model 3 mask 3
- */
-- if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
-+ if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
- clear_cpu_cap(c, X86_FEATURE_SEP);
-
- /*
-@@ -367,7 +367,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- * P4 Xeon erratum 037 workaround.
- * Hardware prefetcher may cause stale data to be loaded into the cache.
- */
-- if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-+ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
- if (msr_set_bit(MSR_IA32_MISC_ENABLE,
- MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
- pr_info("CPU: C0 stepping P4 Xeon detected.\n");
-@@ -382,7 +382,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- * Specification Update").
- */
- if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
-- (c->x86_mask < 0x6 || c->x86_mask == 0xb))
-+ (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
- set_cpu_bug(c, X86_BUG_11AP);
-
-
-@@ -601,7 +601,7 @@ static void init_intel(struct cpuinfo_x86 *c)
- case 6:
- if (l2 == 128)
- p = "Celeron (Mendocino)";
-- else if (c->x86_mask == 0 || c->x86_mask == 5)
-+ else if (c->x86_stepping == 0 || c->x86_stepping == 5)
- p = "Celeron-A";
- break;
-
-diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
-index cdc0dea..5d346c0 100644
---- a/arch/x86/kernel/cpu/microcode/intel.c
-+++ b/arch/x86/kernel/cpu/microcode/intel.c
-@@ -1055,7 +1055,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
- enum ucode_state ret;
-
- sprintf(name, "intel-ucode/%02x-%02x-%02x",
-- c->x86, c->x86_model, c->x86_mask);
-+ c->x86, c->x86_model, c->x86_stepping);
-
- if (request_firmware_direct(&firmware, name, device)) {
- pr_debug("data file %s load failed\n", name);
-diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
-index fdc5521..e12ee86 100644
---- a/arch/x86/kernel/cpu/mtrr/generic.c
-+++ b/arch/x86/kernel/cpu/mtrr/generic.c
-@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
- */
- if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
- boot_cpu_data.x86_model == 1 &&
-- boot_cpu_data.x86_mask <= 7) {
-+ boot_cpu_data.x86_stepping <= 7) {
- if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
- pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
- return -EINVAL;
-diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
-index 24e87e7..fae740c 100644
---- a/arch/x86/kernel/cpu/mtrr/main.c
-+++ b/arch/x86/kernel/cpu/mtrr/main.c
-@@ -699,8 +699,8 @@ void __init mtrr_bp_init(void)
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- boot_cpu_data.x86 == 0xF &&
- boot_cpu_data.x86_model == 0x3 &&
-- (boot_cpu_data.x86_mask == 0x3 ||
-- boot_cpu_data.x86_mask == 0x4))
-+ (boot_cpu_data.x86_stepping == 0x3 ||
-+ boot_cpu_data.x86_stepping == 0x4))
- phys_addr = 36;
-
- size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
-diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
-index 18ca99f..9e817f2 100644
---- a/arch/x86/kernel/cpu/proc.c
-+++ b/arch/x86/kernel/cpu/proc.c
-@@ -70,8 +70,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
- c->x86_model,
- c->x86_model_id[0] ? c->x86_model_id : "unknown");
-
-- if (c->x86_mask || c->cpuid_level >= 0)
-- seq_printf(m, "stepping\t: %d\n", c->x86_mask);
-+ if (c->x86_stepping || c->cpuid_level >= 0)
-+ seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
- else
- seq_puts(m, "stepping\t: unknown\n");
- if (c->microcode)
-diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
-index 2dabea4..82155d0 100644
---- a/arch/x86/kernel/head_32.S
-+++ b/arch/x86/kernel/head_32.S
-@@ -35,7 +35,7 @@
- #define X86 new_cpu_data+CPUINFO_x86
- #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
- #define X86_MODEL new_cpu_data+CPUINFO_x86_model
--#define X86_MASK new_cpu_data+CPUINFO_x86_mask
-+#define X86_STEPPING new_cpu_data+CPUINFO_x86_stepping
- #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
- #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
- #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
-@@ -441,7 +441,7 @@ enable_paging:
- shrb $4,%al
- movb %al,X86_MODEL
- andb $0x0f,%cl # mask mask revision
-- movb %cl,X86_MASK
-+ movb %cl,X86_STEPPING
- movl %edx,X86_CAPABILITY
-
- is486:
-diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
-index 0f8d204..d0fb941 100644
---- a/arch/x86/kernel/mpparse.c
-+++ b/arch/x86/kernel/mpparse.c
-@@ -406,7 +406,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
- processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
- processor.cpuflag = CPU_ENABLED;
- processor.cpufeature = (boot_cpu_data.x86 << 8) |
-- (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
-+ (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
- processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
- processor.reserved[0] = 0;
- processor.reserved[1] = 0;
-diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
-index d6f848d..2dd1fe13 100644
---- a/arch/x86/lib/cpu.c
-+++ b/arch/x86/lib/cpu.c
-@@ -18,7 +18,7 @@ unsigned int x86_model(unsigned int sig)
- {
- unsigned int fam, model;
-
-- fam = x86_family(sig);
-+ fam = x86_family(sig);
-
- model = (sig >> 4) & 0xf;
-
-diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
-index 44ce806..e278125 100644
---- a/drivers/char/hw_random/via-rng.c
-+++ b/drivers/char/hw_random/via-rng.c
-@@ -166,7 +166,7 @@ static int via_rng_init(struct hwrng *rng)
- /* Enable secondary noise source on CPUs where it is present. */
-
- /* Nehemiah stepping 8 and higher */
-- if ((c->x86_model == 9) && (c->x86_mask > 7))
-+ if ((c->x86_model == 9) && (c->x86_stepping > 7))
- lo |= VIA_NOISESRC2;
-
- /* Esther */
-diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
-index 297e912..1ee3674 100644
---- a/drivers/cpufreq/acpi-cpufreq.c
-+++ b/drivers/cpufreq/acpi-cpufreq.c
-@@ -648,7 +648,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c)
- if (c->x86_vendor == X86_VENDOR_INTEL) {
- if ((c->x86 == 15) &&
- (c->x86_model == 6) &&
-- (c->x86_mask == 8)) {
-+ (c->x86_stepping == 8)) {
- pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n");
- return -ENODEV;
- }
-diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
-index c46a12d..d5e27bc 100644
---- a/drivers/cpufreq/longhaul.c
-+++ b/drivers/cpufreq/longhaul.c
-@@ -775,7 +775,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- break;
-
- case 7:
-- switch (c->x86_mask) {
-+ switch (c->x86_stepping) {
- case 0:
- longhaul_version = TYPE_LONGHAUL_V1;
- cpu_model = CPU_SAMUEL2;
-@@ -787,7 +787,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- break;
- case 1 ... 15:
- longhaul_version = TYPE_LONGHAUL_V2;
-- if (c->x86_mask < 8) {
-+ if (c->x86_stepping < 8) {
- cpu_model = CPU_SAMUEL2;
- cpuname = "C3 'Samuel 2' [C5B]";
- } else {
-@@ -814,7 +814,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- numscales = 32;
- memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
- memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
-- switch (c->x86_mask) {
-+ switch (c->x86_stepping) {
- case 0 ... 1:
- cpu_model = CPU_NEHEMIAH;
- cpuname = "C3 'Nehemiah A' [C5XLOE]";
-diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c
-index fd77812..a25741b 100644
---- a/drivers/cpufreq/p4-clockmod.c
-+++ b/drivers/cpufreq/p4-clockmod.c
-@@ -168,7 +168,7 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
- #endif
-
- /* Errata workaround */
-- cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
-+ cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
- switch (cpuid) {
- case 0x0f07:
- case 0x0f0a:
-diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
-index 9f013ed..ef276f6 100644
---- a/drivers/cpufreq/powernow-k7.c
-+++ b/drivers/cpufreq/powernow-k7.c
-@@ -131,7 +131,7 @@ static int check_powernow(void)
- return 0;
- }
-
-- if ((c->x86_model == 6) && (c->x86_mask == 0)) {
-+ if ((c->x86_model == 6) && (c->x86_stepping == 0)) {
- pr_info("K7 660[A0] core detected, enabling errata workarounds\n");
- have_a0 = 1;
- }
-diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
-index 41bc539..4fa5adf 100644
---- a/drivers/cpufreq/speedstep-centrino.c
-+++ b/drivers/cpufreq/speedstep-centrino.c
-@@ -37,7 +37,7 @@ struct cpu_id
- {
- __u8 x86; /* CPU family */
- __u8 x86_model; /* model */
-- __u8 x86_mask; /* stepping */
-+ __u8 x86_stepping; /* stepping */
- };
-
- enum {
-@@ -277,7 +277,7 @@ static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
- {
- if ((c->x86 == x->x86) &&
- (c->x86_model == x->x86_model) &&
-- (c->x86_mask == x->x86_mask))
-+ (c->x86_stepping == x->x86_stepping))
- return 1;
- return 0;
- }
-diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
-index 1b80621..ade98a2 100644
---- a/drivers/cpufreq/speedstep-lib.c
-+++ b/drivers/cpufreq/speedstep-lib.c
-@@ -272,9 +272,9 @@ unsigned int speedstep_detect_processor(void)
- ebx = cpuid_ebx(0x00000001);
- ebx &= 0x000000FF;
-
-- pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
-+ pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
-
-- switch (c->x86_mask) {
-+ switch (c->x86_stepping) {
- case 4:
- /*
- * B-stepping [M-P4-M]
-@@ -361,7 +361,7 @@ unsigned int speedstep_detect_processor(void)
- msr_lo, msr_hi);
- if ((msr_hi & (1<<18)) &&
- (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
-- if (c->x86_mask == 0x01) {
-+ if (c->x86_stepping == 0x01) {
- pr_debug("early PIII version\n");
- return SPEEDSTEP_CPU_PIII_C_EARLY;
- } else
-diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
-index 441e86b..9126627 100644
---- a/drivers/crypto/padlock-aes.c
-+++ b/drivers/crypto/padlock-aes.c
-@@ -531,7 +531,7 @@ static int __init padlock_init(void)
-
- printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
-
-- if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
-+ if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
- ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
- cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
- printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
-diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
-index 82dab16..3cb3e8b 100644
---- a/drivers/edac/amd64_edac.c
-+++ b/drivers/edac/amd64_edac.c
-@@ -3150,7 +3150,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
- struct amd64_family_type *fam_type = NULL;
-
- pvt->ext_model = boot_cpu_data.x86_model >> 4;
-- pvt->stepping = boot_cpu_data.x86_mask;
-+ pvt->stepping = boot_cpu_data.x86_stepping;
- pvt->model = boot_cpu_data.x86_model;
- pvt->fam = boot_cpu_data.x86;
-
-diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
-index 3af92fc..3d5436f 100644
---- a/drivers/edac/mce_amd.c
-+++ b/drivers/edac/mce_amd.c
-@@ -949,7 +949,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
-
- pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
- m->extcpu,
-- c->x86, c->x86_model, c->x86_mask,
-+ c->x86, c->x86_model, c->x86_stepping,
- m->bank,
- ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
- ((m->status & MCI_STATUS_UC) ? "UE" :
-diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
-index 6a27eb2..be1e380 100644
---- a/drivers/hwmon/coretemp.c
-+++ b/drivers/hwmon/coretemp.c
-@@ -269,13 +269,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
- for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
- const struct tjmax_model *tm = &tjmax_model_table[i];
- if (c->x86_model == tm->model &&
-- (tm->mask == ANY || c->x86_mask == tm->mask))
-+ (tm->mask == ANY || c->x86_stepping == tm->mask))
- return tm->tjmax;
- }
-
- /* Early chips have no MSR for TjMax */
-
-- if (c->x86_model == 0xf && c->x86_mask < 4)
-+ if (c->x86_model == 0xf && c->x86_stepping < 4)
- usemsr_ee = 0;
-
- if (c->x86_model > 0xe && usemsr_ee) {
-@@ -426,7 +426,7 @@ static int chk_ucode_version(unsigned int cpu)
- * Readings might stop update when processor visited too deep sleep,
- * fixed for stepping D0 (6EC).
- */
-- if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
-+ if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
- pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
- return -ENODEV;
- }
-diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
-index ef91b8a..84e9128 100644
---- a/drivers/hwmon/hwmon-vid.c
-+++ b/drivers/hwmon/hwmon-vid.c
-@@ -293,7 +293,7 @@ u8 vid_which_vrm(void)
- if (c->x86 < 6) /* Any CPU with family lower than 6 */
- return 0; /* doesn't have VID */
-
-- vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
-+ vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
- if (vrm_ret == 134)
- vrm_ret = get_via_model_d_vrm();
- if (vrm_ret == 0)
-diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
-index 9cdfde6..0124584 100644
---- a/drivers/hwmon/k10temp.c
-+++ b/drivers/hwmon/k10temp.c
-@@ -179,7 +179,7 @@ static bool has_erratum_319(struct pci_dev *pdev)
- * and AM3 formats, but that's the best we can do.
- */
- return boot_cpu_data.x86_model < 4 ||
-- (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
-+ (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
- }
-
- static int k10temp_probe(struct pci_dev *pdev,
-diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
-index 734d55d..4865027 100644
---- a/drivers/hwmon/k8temp.c
-+++ b/drivers/hwmon/k8temp.c
-@@ -187,7 +187,7 @@ static int k8temp_probe(struct pci_dev *pdev,
- return -ENOMEM;
-
- model = boot_cpu_data.x86_model;
-- stepping = boot_cpu_data.x86_mask;
-+ stepping = boot_cpu_data.x86_stepping;
-
- /* feature available since SH-C0, exclude older revisions */
- if ((model == 4 && stepping == 0) ||
-diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
-index 6082f65..67773e8 100644
---- a/drivers/video/fbdev/geode/video_gx.c
-+++ b/drivers/video/fbdev/geode/video_gx.c
-@@ -127,7 +127,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
- int timeout = 1000;
-
- /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
-- if (cpu_data(0).x86_mask == 1) {
-+ if (cpu_data(0).x86_stepping == 1) {
- pll_table = gx_pll_table_14MHz;
- pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
- } else {
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-27 11:00:03 +0000