diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5604-drm-amd-display-Raise-dispclk-value-for-Polaris.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5604-drm-amd-display-Raise-dispclk-value-for-Polaris.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5604-drm-amd-display-Raise-dispclk-value-for-Polaris.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5604-drm-amd-display-Raise-dispclk-value-for-Polaris.patch new file mode 100644 index 00000000..5e2ecd04 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5604-drm-amd-display-Raise-dispclk-value-for-Polaris.patch @@ -0,0 +1,47 @@ +From 74b4b9a2b34d3f34b509427e16c4ede8ea5f22e2 Mon Sep 17 00:00:00 2001 +From: Roman Li <Roman.Li@amd.com> +Date: Tue, 20 Nov 2018 16:50:29 -0500 +Subject: [PATCH 5604/5725] drm/amd/display: Raise dispclk value for Polaris + +[Why] +The visual corruption due to low display clock value. +Observed on RHEL7.6/Polaris at 2K@120Hz. + +[How] +There was earlier patch for dspclk: +'drm/amd/display: Raise dispclk value for dce_update_clocks' +Adding +15% workaround also to to dce112_update_clocks + +Signed-off-by: Roman Li <Roman.Li@amd.com> +Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +index 02ddc94..f1e71a8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +@@ -668,6 +668,10 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr, + { + struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); + struct dm_pp_power_level_change_request level_change_req; ++ int unpatched_disp_clk = context->bw.dce.dispclk_khz; ++ ++ if (!clk_mgr_dce->dfs_bypass_active) ++ context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; + + level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); + /* get max clock state from PPLIB */ +@@ -682,6 +686,8 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr, + clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz; + } + dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); ++ ++ context->bw.dce.dispclk_khz = unpatched_disp_clk; + } + + static void dce12_update_clocks(struct clk_mgr *clk_mgr, +-- +2.7.4 + |