diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4669-drm-amd-pp-Update-clk-with-od-setting-when-set-power.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4669-drm-amd-pp-Update-clk-with-od-setting-when-set-power.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4669-drm-amd-pp-Update-clk-with-od-setting-when-set-power.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4669-drm-amd-pp-Update-clk-with-od-setting-when-set-power.patch new file mode 100644 index 00000000..b1b37ff1 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4669-drm-amd-pp-Update-clk-with-od-setting-when-set-power.patch @@ -0,0 +1,48 @@ +From 13edfac5ad0e424772244f3b03974020c110835b Mon Sep 17 00:00:00 2001 +From: Rex Zhu <rex.zhu@amd.com> +Date: Thu, 19 Jul 2018 16:32:05 +0800 +Subject: [PATCH 4669/5725] drm/amd/pp: Update clk with od setting when set + power state + +This can fix the issue resume from S3, the user's OD setting +were reverted to default. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 79f96a1..8be5a71 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -3268,10 +3268,25 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + { + int result = 0; + struct vega10_hwmgr *data = hwmgr->backend; ++ struct vega10_dpm_table *dpm_table = &data->dpm_table; ++ struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; ++ struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; ++ int count; + + if (!data->need_update_dpm_table) + return 0; + ++ if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { ++ for (count = 0; count < dpm_table->gfx_table.count; count++) ++ dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; ++ } ++ ++ odn_clk_table = &odn_table->vdd_dep_on_mclk; ++ if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { ++ for (count = 0; count < dpm_table->mem_table.count; count++) ++ dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; ++ } ++ + if (data->need_update_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) { + result = vega10_populate_all_graphic_levels(hwmgr); +-- +2.7.4 + |