diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4417-drm-amd-display-Remove-COMBO_DISPLAY_PLL0-from-Vega2.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4417-drm-amd-display-Remove-COMBO_DISPLAY_PLL0-from-Vega2.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4417-drm-amd-display-Remove-COMBO_DISPLAY_PLL0-from-Vega2.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4417-drm-amd-display-Remove-COMBO_DISPLAY_PLL0-from-Vega2.patch new file mode 100644 index 00000000..c63951ea --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4417-drm-amd-display-Remove-COMBO_DISPLAY_PLL0-from-Vega2.patch @@ -0,0 +1,68 @@ +From c1bdeb4c0296d7092c2f1a12f308b77ec45f1be4 Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Fri, 20 Apr 2018 21:03:10 +0800 +Subject: [PATCH 4417/5725] drm/amd/display: Remove COMBO_DISPLAY_PLL0 from + Vega20 + +Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> +Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 11 ++++++++++- + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 ++++++ + 2 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +index 78e6beb..aa4cf30 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +@@ -35,7 +35,7 @@ + #endif + #include "core_types.h" + #include "dc_types.h" +- ++#include "dal_asic_id.h" + + #define TO_DCE_CLOCKS(clocks)\ + container_of(clocks, struct dce_disp_clk, base) +@@ -413,9 +413,18 @@ static int dce112_set_clock( + /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ + dce_clk_params.target_clock_frequency = 0; + dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; ++#ifndef CONFIG_DRM_AMD_DC_VG20 + dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = + (dce_clk_params.pll_id == + CLOCK_SOURCE_COMBO_DISPLAY_PLL0); ++#else ++ if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev)) ++ dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = ++ (dce_clk_params.pll_id == ++ CLOCK_SOURCE_COMBO_DISPLAY_PLL0); ++ else ++ dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; ++#endif + + bp->funcs->set_dce_clock(bp, &dce_clk_params); + +diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h +index 1b987b6..77d2856 100644 +--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h ++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h +@@ -117,6 +117,12 @@ + ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) + + /* DCE12 */ ++#define AI_UNKNOWN 0xFF ++ ++#ifdef CONFIG_DRM_AMD_DC_VG20 ++#define AI_VEGA20_P_A0 40 ++#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) ++#endif + + #define AI_GREENLAND_P_A0 1 + #define AI_GREENLAND_P_A1 2 +-- +2.7.4 + |