diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4246-drm-amdgpu-pm-document-pp_od_clk_voltage.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4246-drm-amdgpu-pm-document-pp_od_clk_voltage.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4246-drm-amdgpu-pm-document-pp_od_clk_voltage.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4246-drm-amdgpu-pm-document-pp_od_clk_voltage.patch new file mode 100644 index 00000000..48c548a3 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4246-drm-amdgpu-pm-document-pp_od_clk_voltage.patch @@ -0,0 +1,51 @@ +From 51b14036234ae03f676aaf09dc1d23eab5b83928 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 19 Apr 2018 14:59:55 -0500 +Subject: [PATCH 4246/5725] drm/amdgpu/pm: document pp_od_clk_voltage + +sysfs interface for fine grained clock and voltage control. + +Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +index 3345760..4cbce49 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +@@ -455,6 +455,29 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, + return count; + } + ++/** ++ * DOC: pp_od_clk_voltage ++ * ++ * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages ++ * in each power level within a power state. The pp_od_clk_voltage is used for ++ * this. ++ * ++ * Reading the file will display: ++ * - a list of engine clock levels and voltages labeled OD_SCLK ++ * - a list of memory clock levels and voltages labeled OD_MCLK ++ * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE ++ * ++ * To manually adjust these settings, first select manual using ++ * power_dpm_force_performance_level. Enter a new value for each ++ * level by writing a string that contains "s/m level clock voltage" to ++ * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz ++ * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at ++ * 810 mV. When you have edited all of the states as needed, write ++ * "c" (commit) to the file to commit your changes. If you want to reset to the ++ * default power levels, write "r" (reset) to the file to reset them. ++ * ++ */ ++ + static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, + struct device_attribute *attr, + const char *buf, +-- +2.7.4 + |