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-rw-r--r--common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch161
1 files changed, 161 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch b/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch
new file mode 100644
index 00000000..18c20545
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch
@@ -0,0 +1,161 @@
+From 46a67a9539b62458ba7c124a7e2efc3fe2ad271a Mon Sep 17 00:00:00 2001
+From: Mykola Lysenko <Mykola.Lysenko@amd.com>
+Date: Fri, 19 Feb 2016 06:05:08 -0500
+Subject: [PATCH 0835/1110] drm/amd/dal: allow DP non-external clock source
+ sharing
+
+In case external clock source is not available DP connections
+could use one PLL
+
+Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 3 ++-
+ drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 1 +
+ drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 5 +++--
+ drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 12 ++++++------
+ drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 14 ++++++++++----
+ drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 1 +
+ 6 files changed, 23 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+index 054216c..88a4eb9 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+@@ -1151,8 +1151,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
+ /* get link settings for video mode timing */
+ decide_link_settings(stream, &link_settings);
+ dp_enable_link_phy(
+- stream->sink->link,
++ link,
+ pipe_ctx->signal,
++ pipe_ctx->clock_source->id,
+ &link_settings);
+
+ panel_mode = dp_get_panel_mode(link);
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+index ed2add8..e5a63f4 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+@@ -1137,6 +1137,7 @@ bool dp_hbr_verify_link_cap(
+ dp_enable_link_phy(
+ link,
+ link->public.connector_signal,
++ CLOCK_SOURCE_ID_UNDEFINED,
+ cur);
+
+ if (skip_link_training)
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+index f332185..3f05723 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+@@ -54,6 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
+ void dp_enable_link_phy(
+ struct core_link *link,
+ enum signal_type signal,
++ enum clock_source_id clock_source,
+ const struct dc_link_settings *link_settings)
+ {
+ struct link_encoder *link_enc = link->link_enc;
+@@ -67,12 +68,12 @@ void dp_enable_link_phy(
+ link_enc->funcs->enable_dp_output(
+ link_enc,
+ link_settings,
+- CLOCK_SOURCE_ID_EXTERNAL);
++ clock_source);
+ } else {
+ link_enc->funcs->enable_dp_mst_output(
+ link_enc,
+ link_settings,
+- CLOCK_SOURCE_ID_EXTERNAL);
++ clock_source);
+ }
+
+ dp_receiver_power_ctrl(link, true);
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+index 03a3161..42c456a 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+@@ -106,7 +106,6 @@ static bool is_sharable_clk_src(
+ const struct pipe_ctx *pipe_with_clk_src,
+ const struct pipe_ctx *pipe)
+ {
+- enum clock_source_id id = pipe_with_clk_src->clock_source->id;
+ #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+ enum dce_version dce_ver = dal_adapter_service_get_dce_version(
+ pipe->stream->sink->link->adapter_srv);
+@@ -114,14 +113,18 @@ static bool is_sharable_clk_src(
+ /* Currently no clocks are shared for DCE 10 until VBIOS behaviour
+ * is verified for this use case
+ */
+- if (dce_ver == DCE_VERSION_10_0)
++ if (dce_ver == DCE_VERSION_10_0 && !dc_is_dp_signal(pipe->signal))
+ return false;
+ #endif
+
+ if (pipe_with_clk_src->clock_source == NULL)
+ return false;
+
+- if (id == CLOCK_SOURCE_ID_EXTERNAL)
++ if (dc_is_dp_signal(pipe->signal) &&
++ dc_is_dp_signal(pipe_with_clk_src->signal))
++ return true;
++
++ if (pipe->signal != pipe_with_clk_src->signal)
+ return false;
+
+ if(!is_same_timing(
+@@ -139,9 +142,6 @@ struct clock_source *find_used_clk_src_for_sharing(
+ uint8_t i;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+- if (res_ctx->pipe_ctx[i].clock_source == NULL)
+- continue;
+-
+ if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
+ return res_ctx->pipe_ctx[i].clock_source;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+index d2ea0a0..c7145c5 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+@@ -841,14 +841,20 @@ static enum dc_status map_clock_resources(
+ if (context->res_ctx.pipe_ctx[k].stream != stream)
+ continue;
+
++ /*
++ * in this case if external clock source is not
++ * available for DP, it will pick-up first
++ * available pll from find_first_free_pll
++ */
+ if (dc_is_dp_signal(pipe_ctx->signal)
+ || pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
+- pipe_ctx->clock_source = context->res_ctx.
+- pool.clock_sources[DCE100_CLK_SRC_EXT];
+- else
++ pipe_ctx->clock_source = context->res_ctx.pool.clock_sources[DCE100_CLK_SRC_EXT];
++
++ if (pipe_ctx->clock_source == NULL)
+ pipe_ctx->clock_source =
+ find_used_clk_src_for_sharing(
+- &context->res_ctx, pipe_ctx);
++ &context->res_ctx,
++ pipe_ctx);
+
+ if (pipe_ctx->clock_source == NULL)
+ pipe_ctx->clock_source =
+diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
+index d56b5d1..d4d9084 100644
+--- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
++++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
+@@ -43,6 +43,7 @@ enum dc_status core_link_write_dpcd(
+ void dp_enable_link_phy(
+ struct core_link *link,
+ enum signal_type signal,
++ enum clock_source_id clock_source,
+ const struct dc_link_settings *link_settings);
+
+ void dp_receiver_power_ctrl(struct core_link *link, bool on);
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-05 17:57:11 +0000