diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch b/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch new file mode 100644 index 00000000..3559e0a0 --- /dev/null +++ b/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch @@ -0,0 +1,117 @@ +From 094b9b451f4889c854def2e9fc9343c5a40cc9da Mon Sep 17 00:00:00 2001 +From: Vitaly Prosyak <vitaly.prosyak@amd.com> +Date: Fri, 18 Mar 2016 15:49:41 -0400 +Subject: [PATCH 0446/1110] drm/amdgpu/dce11: fix vertical bars appear on + monitor + +Fixed mc stop and resume hardware programming sequence. + +Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 65 +++------------------------------- + 1 file changed, 5 insertions(+), 60 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index ad43347..fd74bce 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -565,35 +565,14 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, + crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), + CRTC_CONTROL, CRTC_MASTER_EN); + if (crtc_enabled) { +-#if 0 +- u32 frame_count; +- int j; +- ++#if 1 + save->crtc_enabled[i] = true; + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { +- amdgpu_display_vblank_wait(adev, i); +- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); ++ /*it is correct only for RGB ; black is 0*/ ++ WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); +- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); +- } +- /* wait for the next frame */ +- frame_count = amdgpu_display_vblank_get_counter(adev, i); +- for (j = 0; j < adev->usec_timeout; j++) { +- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) +- break; +- udelay(1); +- } +- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { +- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); +- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); +- } +- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { +- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); +- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } + #else + /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ +@@ -614,54 +593,20 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, + static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) + { +- u32 tmp, frame_count; +- int i, j; ++ u32 tmp; ++ int i; + + /* update crtc base addresses */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); +- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], +- upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); +- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], +- (u32)adev->mc.vram_start); + + if (save->crtc_enabled[i]) { +- tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { +- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); +- WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); +- } +- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { +- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); +- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); +- } +- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { +- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); +- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); +- } +- for (j = 0; j < adev->usec_timeout; j++) { +- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); +- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) +- break; +- udelay(1); +- } + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); +- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); +- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); +- /* wait for the next frame */ +- frame_count = amdgpu_display_vblank_get_counter(adev, i); +- for (j = 0; j < adev->usec_timeout; j++) { +- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) +- break; +- udelay(1); +- } + } + } + +-- +2.7.4 + |