diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch b/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch new file mode 100644 index 00000000..576e7bfb --- /dev/null +++ b/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch @@ -0,0 +1,115 @@ +From c3072891a30b09fe18f262f11ebef70913c232cc Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 12 Feb 2016 03:22:34 -0500 +Subject: [PATCH 0315/1110] drm/amdgpu/vi: move uvd tiling config setup into + uvd code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Split uvd and gfx programming. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ------------ + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 10 ++++++++++ + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 10 ++++++++++ + 3 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 13eb40f..1744f67 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -43,9 +43,6 @@ + #include "gca/gfx_8_0_sh_mask.h" + #include "gca/gfx_8_0_enum.h" + +-#include "uvd/uvd_5_0_d.h" +-#include "uvd/uvd_5_0_sh_mask.h" +- + #include "dce/dce_10_0_d.h" + #include "dce/dce_10_0_sh_mask.h" + +@@ -2695,9 +2692,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) + WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); +- WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); +- WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); +- WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + + gfx_v8_0_tiling_mode_table_init(adev); + +@@ -3955,12 +3949,6 @@ static void gfx_v8_0_print_status(void *handle) + RREG32(mmHDP_ADDR_CONFIG)); + dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", + RREG32(mmDMIF_ADDR_CALC)); +- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", +- RREG32(mmUVD_UDEC_ADDR_CONFIG)); +- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", +- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); +- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", +- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + + dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", + RREG32(mmCP_MEQ_THRESHOLDS)); +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +index c5edb98..e3c852d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -279,6 +279,10 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) + size = AMDGPU_UVD_HEAP_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE2, size); ++ ++ WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); ++ WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); ++ WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + } + + /** +@@ -724,6 +728,12 @@ static void uvd_v5_0_print_status(void *handle) + RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", + RREG32(mmUVD_CONTEXT_ID)); ++ dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_ADDR_CONFIG)); ++ dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); ++ dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + } + + static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index 0d5098e..3375e61 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -277,6 +277,10 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) + size = AMDGPU_UVD_HEAP_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE2, size); ++ ++ WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); ++ WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); ++ WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + } + + static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, +@@ -947,6 +951,12 @@ static void uvd_v6_0_print_status(void *handle) + RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", + RREG32(mmUVD_CONTEXT_ID)); ++ dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_ADDR_CONFIG)); ++ dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); ++ dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", ++ RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + } + + static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, +-- +2.7.4 + |