summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/sh73a0.dtsi
blob: ff7c8f298f30a58d3ea987f2375acfe3f6e9be34 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
/*
 * Device Tree Source for the SH73A0 SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,sh73a0";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1196000000>;
			power-domains = <&pd_a2sl>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1196000000>;
			power-domains = <&pd_a2sl>;
		};
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		clocks = <&twd_clk>;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	sbsc2: memory-controller@fb400000 {
		compatible = "renesas,sbsc-sh73a0";
		reg = <0xfb400000 0x400>;
		interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sec", "temp";
		power-domains = <&pd_a4bc1>;
	};

	sbsc1: memory-controller@fe400000 {
		compatible = "renesas,sbsc-sh73a0";
		reg = <0xfe400000 0x400>;
		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
			     <0 36 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sec", "temp";
		power-domains = <&pd_a4bc0>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
			     <0 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	cmt1: timer@e6138000 {
		compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
		reg = <0xe6138000 0x200>;
		interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
		clock-names = "fck";
		power-domains = <&pd_c5>;

		renesas,channels-mask = <0x3f>;

		status = "disabled";
	};

	irqpin0: interrupt-controller@e6900000 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900000 4>,
			<0xe6900010 4>,
			<0xe6900020 1>,
			<0xe6900040 1>,
			<0xe6900060 1>;
		interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
			      0 2 IRQ_TYPE_LEVEL_HIGH
			      0 3 IRQ_TYPE_LEVEL_HIGH
			      0 4 IRQ_TYPE_LEVEL_HIGH
			      0 5 IRQ_TYPE_LEVEL_HIGH
			      0 6 IRQ_TYPE_LEVEL_HIGH
			      0 7 IRQ_TYPE_LEVEL_HIGH
			      0 8 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin1: interrupt-controller@e6900004 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900004 4>,
			<0xe6900014 4>,
			<0xe6900024 1>,
			<0xe6900044 1>,
			<0xe6900064 1>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
			      0 10 IRQ_TYPE_LEVEL_HIGH
			      0 11 IRQ_TYPE_LEVEL_HIGH
			      0 12 IRQ_TYPE_LEVEL_HIGH
			      0 13 IRQ_TYPE_LEVEL_HIGH
			      0 14 IRQ_TYPE_LEVEL_HIGH
			      0 15 IRQ_TYPE_LEVEL_HIGH
			      0 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin2: interrupt-controller@e6900008 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900008 4>,
			<0xe6900018 4>,
			<0xe6900028 1>,
			<0xe6900048 1>,
			<0xe6900068 1>;
		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
			      0 18 IRQ_TYPE_LEVEL_HIGH
			      0 19 IRQ_TYPE_LEVEL_HIGH
			      0 20 IRQ_TYPE_LEVEL_HIGH
			      0 21 IRQ_TYPE_LEVEL_HIGH
			      0 22 IRQ_TYPE_LEVEL_HIGH
			      0 23 IRQ_TYPE_LEVEL_HIGH
			      0 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin3: interrupt-controller@e690000c {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe690000c 4>,
			<0xe690001c 4>,
			<0xe690002c 1>,
			<0xe690004c 1>,
			<0xe690006c 1>;
		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
			      0 26 IRQ_TYPE_LEVEL_HIGH
			      0 27 IRQ_TYPE_LEVEL_HIGH
			      0 28 IRQ_TYPE_LEVEL_HIGH
			      0 29 IRQ_TYPE_LEVEL_HIGH
			      0 30 IRQ_TYPE_LEVEL_HIGH
			      0 31 IRQ_TYPE_LEVEL_HIGH
			      0 32 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	i2c0: i2c@e6820000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6820000 0x425>;
		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
			      0 168 IRQ_TYPE_LEVEL_HIGH
			      0 169 IRQ_TYPE_LEVEL_HIGH
			      0 170 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c1: i2c@e6822000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6822000 0x425>;
		interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
			      0 52 IRQ_TYPE_LEVEL_HIGH
			      0 53 IRQ_TYPE_LEVEL_HIGH
			      0 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c2: i2c@e6824000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6824000 0x425>;
		interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
			      0 172 IRQ_TYPE_LEVEL_HIGH
			      0 173 IRQ_TYPE_LEVEL_HIGH
			      0 174 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c3: i2c@e6826000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6826000 0x425>;
		interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
			      0 184 IRQ_TYPE_LEVEL_HIGH
			      0 185 IRQ_TYPE_LEVEL_HIGH
			      0 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c4: i2c@e6828000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6828000 0x425>;
		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
			      0 188 IRQ_TYPE_LEVEL_HIGH
			      0 189 IRQ_TYPE_LEVEL_HIGH
			      0 190 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
		power-domains = <&pd_c5>;
		status = "disabled";
	};

	mmcif: mmc@e6bd0000 {
		compatible = "renesas,sh-mmcif";
		reg = <0xe6bd0000 0x100>;
		interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
			      0 141 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
		power-domains = <&pd_a3sp>;
		reg-io-width = <4>;
		status = "disabled";
	};

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee100000 0x100>;
		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
			      0 84 IRQ_TYPE_LEVEL_HIGH
			      0 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		status = "disabled";
	};

	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
	sdhi1: sd@ee120000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee120000 0x100>;
		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
			      0 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
		power-domains = <&pd_a3sp>;
		toshiba,mmc-wrprotect-disable;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: sd@ee140000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee140000 0x100>;
		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
			      0 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
		power-domains = <&pd_a3sp>;
		toshiba,mmc-wrprotect-disable;
		cap-sd-highspeed;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c40000 0x100>;
		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c50000 0x100>;
		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c60000 0x100>;
		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c70000 0x100>;
		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa4: serial@e6c80000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c80000 0x100>;
		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa5: serial@e6cb0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cb0000 0x100>;
		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa6: serial@e6cc0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cc0000 0x100>;
		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa7: serial@e6cd0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cd0000 0x100>;
		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb: serial@e6c30000 {
		compatible = "renesas,scifb-sh73a0", "renesas,scifb";
		reg = <0xe6c30000 0x100>;
		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
		clock-names = "sci_ick";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	pfc: pfc@e6050000 {
		compatible = "renesas,pfc-sh73a0";
		reg = <0xe6050000 0x8000>,
		      <0xe605801c 0x1c>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges =
			<&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
			<&pfc 288 288 22>;
		interrupts-extended =
			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
		power-domains = <&pd_c5>;
	};

	sysc: system-controller@e6180000 {
		compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
		reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;

		pm-domains {
			pd_c5: c5 {
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				pd_c4: c4@0 {
					reg = <0>;
					#power-domain-cells = <0>;
				};

				pd_d4: d4@1 {
					reg = <1>;
					#power-domain-cells = <0>;
				};

				pd_a4bc0: a4bc0@4 {
					reg = <4>;
					#power-domain-cells = <0>;
				};

				pd_a4bc1: a4bc1@5 {
					reg = <5>;
					#power-domain-cells = <0>;
				};

				pd_a4lc0: a4lc0@6 {
					reg = <6>;
					#power-domain-cells = <0>;
				};

				pd_a4lc1: a4lc1@7 {
					reg = <7>;
					#power-domain-cells = <0>;
				};

				pd_a4mp: a4mp@8 {
					reg = <8>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3mp: a3mp@9 {
						reg = <9>;
						#power-domain-cells = <0>;
					};

					pd_a3vc: a3vc@10 {
						reg = <10>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4rm: a4rm@12 {
					reg = <12>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3r: a3r@13 {
						reg = <13>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2rv: a2rv@14 {
							reg = <14>;
							#address-cells = <1>;
							#size-cells = <0>;
							#power-domain-cells = <0>;
						};
					};
				};

				pd_a4s: a4s@16 {
					reg = <16>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3sp: a3sp@17 {
						reg = <17>;
						#power-domain-cells = <0>;
					};

					pd_a3sg: a3sg@18 {
						reg = <18>;
						#power-domain-cells = <0>;
					};

					pd_a3sm: a3sm@19 {
						reg = <19>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2sl: a2sl@20 {
							reg = <20>;
							#power-domain-cells = <0>;
						};
					};
				};
			};
		};
	};

	sh_fsi2: sound@ec230000 {
		#sound-dai-cells = <1>;
		compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
		reg = <0xec230000 0x400>;
		interrupts = <0 146 0x4>;
		power-domains = <&pd_a4mp>;
		status = "disabled";
	};

	bsc: bus@fec10000 {
		compatible = "renesas,bsc-sh73a0", "renesas,bsc",
			     "simple-pm-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x20000000>;
		reg = <0xfec10000 0x400>;
		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&zb_clk>;
		power-domains = <&pd_a4s>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clocks */
		extalr_clk: extalr_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "extalr";
		};
		extal1_clk: extal1_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
			clock-output-names = "extal1";
		};
		extal2_clk: extal2_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "extal2";
		};
		extcki_clk: extcki_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "extcki";
		};
		fsiack_clk: fsiack_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "fsiack";
		};
		fsibck_clk: fsibck_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "fsibck";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,sh73a0-cpg-clocks";
			reg = <0xe6150000 0x10000>;
			clocks = <&extal1_clk>, <&extal2_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll2",
					     "pll3", "dsi0phy", "dsi1phy",
					     "zg", "m3", "b", "m1", "m2",
					     "z", "zx", "hp";
		};

		/* Variable factor clocks (DIV6) */
		vclk1_clk: vclk1_clk@e6150008 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150008 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
			clock-output-names = "vclk1";
		};
		vclk2_clk: vclk2_clk@e615000c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615000c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
			clock-output-names = "vclk2";
		};
		vclk3_clk: vclk3_clk@e615001c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615001c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
			clock-output-names = "vclk3";
		};
		zb_clk: zb_clk@e6150010 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150010 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "zb";
		};
		flctl_clk: flctl_clk@e6150014 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150014 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "flctlck";
		};
		sdhi0_clk: sdhi0_clk@e6150074 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150074 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
			clock-output-names = "sdhi0ck";
		};
		sdhi1_clk: sdhi1_clk@e6150078 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150078 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
			clock-output-names = "sdhi1ck";
		};
		sdhi2_clk: sdhi2_clk@e615007c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615007c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
			clock-output-names = "sdhi2ck";
		};
		fsia_clk: fsia_clk@e6150018 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150018 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&fsiack_clk>, <&fsiack_clk>;
			#clock-cells = <0>;
			clock-output-names = "fsia";
		};
		fsib_clk: fsib_clk@e6150090 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150090 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&fsibck_clk>, <&fsibck_clk>;
			#clock-cells = <0>;
			clock-output-names = "fsib";
		};
		sub_clk: sub_clk@e6150080 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150080 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sub";
		};
		spua_clk: spua_clk@e6150084 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150084 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
			clock-output-names = "spua";
		};
		spuv_clk: spuv_clk@e6150094 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150094 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
			clock-output-names = "spuv";
		};
		msu_clk: msu_clk@e6150088 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150088 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "msu";
		};
		hsi_clk: hsi_clk@e615008c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615008c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div7_clk>, <0>;
			#clock-cells = <0>;
			clock-output-names = "hsi";
		};
		mfg1_clk: mfg1_clk@e6150098 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150098 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "mfg1";
		};
		mfg2_clk: mfg2_clk@e615009c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615009c 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "mfg2";
		};
		dsit_clk: dsit_clk@e6150060 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150060 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "dsit";
		};
		dsi0p_clk: dsi0p_clk@e6150064 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150064 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
				 <&extcki_clk>, <0>, <0>, <0>;
			#clock-cells = <0>;
			clock-output-names = "dsi0pck";
		};

		/* Fixed factor clocks */
		main_div2_clk: main_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "main_div2";
		};
		pll1_div2_clk: pll1_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "pll1_div2";
		};
		pll1_div7_clk: pll1_div7_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <7>;
			clock-mult = <1>;
			clock-output-names = "pll1_div7";
		};
		pll1_div13_clk: pll1_div13_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <13>;
			clock-mult = <1>;
			clock-output-names = "pll1_div13";
		};
		twd_clk: twd_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "twd";
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@e6150130 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150130 4>, <0xe6150030 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC2
			>;
			clock-output-names =
				"iic2";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150134 4>, <0xe6150038 4>;
			clocks = <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_ZG>,
				 <&cpg_clocks SH73A0_CLK_B>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
				SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
				SH73A0_CLK_TMU0	SH73A0_CLK_DSITX0
				SH73A0_CLK_IIC0 SH73A0_CLK_SGX
				SH73A0_CLK_LCDC0
			>;
			clock-output-names =
				"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
				"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150138 4>, <0xe6150040 4>;
			clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
				SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
				SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
				SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
				SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
			>;
			clock-output-names =
				"scifa7", "sy_dmac", "mp_dmac", "scifa5",
				"scifb", "scifa0", "scifa1", "scifa2",
				"scifa3", "scifa4";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe615013c 4>, <0xe6150048 4>;
			clocks = <&sub_clk>, <&extalr_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
				 <&sdhi0_clk>, <&sdhi1_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
				SH73A0_CLK_FSI SH73A0_CLK_IRDA
				SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
				SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
				SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
				SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
				SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
				SH73A0_CLK_TPU4
			>;
			clock-output-names =
				"scifa6", "cmt1", "fsi", "irda", "iic1",
				"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
				"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150140 4>, <0xe615004c 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
				SH73A0_CLK_KEYSC
			>;
			clock-output-names =
				"iic3", "iic4", "keysc";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150144 4>, <0xe615003c 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_INTCA0
			>;
			clock-output-names =
				"intca0";
		};
	};
};