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Xilinx AXI/PLB soft-core watchdog and window watchdog Device Tree Bindings
--------------------------------------------------------------------------
Required properties:
- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
"xlnx,xps-timebase-wdt-1.01.a" or
"xlnx,versal-wwdt-1.0".
- reg : Physical base address and size
Optional properties:
- clocks : Input clock specifier. Refer to common clock
bindings.
- clock-frequency : Frequency of clock in Hz
Optional properties for AXI/PLB soft-core watchdog:
- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
1 - Watchdog can be enabled just once
- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
<val> is integer from 8 to 31.
Optional properties for window watchdog:
- timeout-sec : Watchdog timeout value (in seconds).
Example:
Xilinx AXI/PLB soft-core watchdog:
axi-timebase-wdt@40100000 {
clock-frequency = <50000000>;
compatible = "xlnx,xps-timebase-wdt-1.00.a";
clocks = <&clkc 15>;
reg = <0x40100000 0x10000>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
} ;
Xilinx Versal window watchdog:
watchdog@fd4d0000 {
compatible = "xlnx,versal-wwdt-1.0";
reg = <0x0 0xfd4d0000 0x0 0x10000>;
clocks = <&clk25>;
timeout-sec = <10>;
} ;
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