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Xilinx VPSS Scaler
------------------------
Required properties:
- compatible: Must be "xlnx,v-vpss-scaler-1.0".
The older string "xlnx,v-vpss-scaler" will be deprecated.
- reg: Physical base address and length of the registers set for the device.
- clocks: Reference to the AXI Streaming clock feeding the VPSS Scaler AP_CLK
and AXI4 Lite control interface clock.
- clock-names: Must contain "aclk_axis" and "aclk_ctrl" in the same order as
clocks listed in clocks property.
- xlnx,num-hori-taps, xlnx,num-vert-taps: The number of horizontal and vertical
taps for scaling filter(range: 2,4,6,8,10,12).
A value of 2 represents bilinear filters. A value of 4 represents bicubic.
Values 6,8,10,12 represent polyphase filters.
- xlnx,pix-per-clk : The pixels per clock property of the IP
- reset-gpios: Specifier for a GPIO that assert for VPSS Scaler reset.
This property is mandatory for the Scaler
- xlnx,max-height: Maximum number of lines.
Valid range from 64 to 4320.
- xlnx,max-width: Maximum number of pixels in a line.
Valid range from 64 to 8192.
- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt.
The scaler has an input port (0) and an output port (1).
Required port properties:
- xlnx,video-format: Must be one of XVIP_VF_RBG or XVIP_VF_YUV_422 for
input port (0) and must be XVIP_VF_RBG or XVIP_VF_YUV_422 or for
the output port (1).
See <dt-bindings/media/xilinx-vip.h> for more details.
- reg: This value represents the media pad of the V4L2 sub-device.
A Sink Pad is represented by reg = <0>
A Source Pad is represented by reg = <1>
- xlnx,video-width: Video width as defined in video.txt
Example:
scaler_1:scaler@a0000000 {
compatible = "xlnx,v-vpss-scaler-1.0";
reg = <0x0 0xa0000000 0x0 0x40000>;
clocks = <&vid_stream_clk>, <&misc_clk_2>;
clock-names = "aclk_axis", "aclk_ctrl";
xlnx,num-hori-taps = <8>;
xlnx,num-vert-taps = <8>;
xlnx,pix-per-clk = <2>;
reset-gpios = <&gpio 87 1>;
xlnx,max-width = <3840>;
xlnx,max-height = <2160>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
/* Sink Pad */
reg = <0>;
xlnx,video-format = <XVIP_VF_RBG>;
xlnx,video-width = <8>;
scaler_in: endpoint {
remote-endpoint = <&csc_out>;
};
};
port@1 {
/* Source Pad */
reg = <1>;
xlnx,video-format = <XVIP_VF_YUV_422>;
xlnx,video-width = <8>;
scaler_out: endpoint {
remote-endpoint = <&vcap_tpg_in>;
};
};
};
};
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