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--------------------------------------------------------------------------
Device Tree Clock bindings for the Xilinx Versal
--------------------------------------------------------------------------
The clock controller is a h/w block of Xilinx versal clock tree. It reads
required input clock frequencies from the devicetree and acts as clock provider
for all clock consumers of PS clocks.
See clock_bindings.txt for more information on the generic clock bindings.
Required properties:
- #clock-cells: Must be 1
- compatible: Must contain: "xlnx,versal-clk"
- clocks: List of clock specifiers which are external input
clocks to the given clock controller. Please refer
the next section to find the input clocks for a
given controller.
- clock-names: List of clock names which are exteral input clocks
to the given clock controller. Please refer to the
clock bindings for more details.
Input clocks for Xilinx Versal clock controller:
The Xilinx Versal has one primary and two alternative reference clock inputs.
These required clock inputs are:
- ref_clk
- alt_ref_clk
- pl_alt_ref_clk
Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
include/dt-bindings/clock/xlnx-versal-clk.h.
-------
Example
-------
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
};
};
};
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