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path: root/include/linux/mfd/intel_soc_pmic.h
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2019-12-01mfd: intel_soc_pmic_bxtwc: Chain power button IRQs as wellAndy Shevchenko
[ Upstream commit 9f8ddee1dab836ca758ca8fc555ab5a3aaa5d3fd ] Power button IRQ actually has a second level of interrupts to distinguish between UI and POWER buttons. Moreover, current implementation looks awkward in approach to handle second level IRQs by first level related IRQ chip. To address above issues, split power button IRQ to be chained as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2017-06-19mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chipsKuppuswamy Sathyanarayanan
Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to mask/unmask individual interrupts belong each of this domain. For example, in case of TMU, at first level we have TMU interrupt domain, and at second level we have two interrupts, wake alarm, system alarm that belong to the TMU interrupt domain. Currently, in this driver all first level IRQs are registered as part of IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ chip from your driver, all IRQs in that chip will masked and can only be enabled if that IRQ is requested using request_irq() call. This is the default Linux IRQ behavior model. And whenever a dependent device that belongs to PMIC requests only the second level IRQ and not explicitly unmask the first level IRQ, then in essence the second level IRQ will still be disabled. For example, if TMU device driver request wake_alarm IRQ and not explicitly unmask TMU level 1 IRQ then according to the default Linux IRQ model, wake_alarm IRQ will still be disabled. So the proper solution to fix this issue is to use the chained IRQ chip concept. We should chain all the second level chip IRQs to the corresponding first level IRQ. To do this, we need to create separate IRQ chips for every group of second level IRQs. In case of TMU, when adding second level IRQ chip, instead of using PMIC IRQ we should use the corresponding first level IRQ. So the following code will change from ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...) to, virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ); ret = regmap_add_irq_chip(pmic->regmap, virq, ...) In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr) to get the USBC virtual IRQ number. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Revieved-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-12-18platform/x86: Add Whiskey Cove PMIC TMU supportNilesh Bacchewar
This adds TMU (Time Management Unit) support for Intel BXT platform. It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove PMIC. Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> [andy: resolve merge conflict in Kconfig] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2015-10-30mfd: intel_soc_pmic: Add support for Broxton WC PMICQipeng Zha
IRQ control registers of Intel Broxton Whisky Cove PMIC are separated in two parts, so add secondary IRQ chip. And the new member of device will be used in PMC IPC regmap APIs. Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-06-17mfd: intel_soc_pmic: Core driverZhu, Lejun
This patch provides the common I2C driver code for Intel SoC PMICs. Signed-off-by: Yang, Bin <bin.yang@intel.com> Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>