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path: root/drivers/net/ethernet/marvell
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2020-09-21Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-09-17octeontx2-af: change (struct qmem)->entry_sz from u8 to u16Eric Dumazet
commit 393415203f5c916b5907e0a7c89f4c2c5a9c5505 upstream. We need to increase TSO_HEADER_SIZE from 128 to 256. Since otx2_sq_init() calls qmem_alloc() with TSO_HEADER_SIZE, we need to change (struct qmem)->entry_sz to avoid truncation to 0. Fixes: 7a37245ef23f ("octeontx2-af: NPA block admin queue init") Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-20Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
2020-08-18net: sky2: initialize return of gm_phy_readTom Rix
commit 28b18e4eb515af7c6661c3995c6e3c34412c2874 upstream. clang static analysis flags this garbage return drivers/net/ethernet/marvell/sky2.c:208:2: warning: Undefined or garbage value returned to caller [core.uninitialized.UndefReturn] return v; ^~~~~~~~ static inline u16 gm_phy_read( ... { u16 v; __gm_phy_read(hw, port, reg, &v); return v; } __gm_phy_read can return without setting v. So handle similar to skge.c's gm_phy_read, initialize v. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-04Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-08-03net: ethernet: mvneta: Do not error out in non serdes modesSascha Hauer
commit d3d239dcb8aae6d7b10642d292b404e57604f7ea upstream. In mvneta_config_interface() the RGMII modes are catched by the default case which is an error return. The RGMII modes are valid modes for the driver, so instead of returning an error add a break statement to return successfully. This avoids this warning for non comphy SoCs which use RGMII, like SolidRun Clearfog: WARNING: CPU: 0 PID: 268 at drivers/net/ethernet/marvell/mvneta.c:3512 mvneta_start_dev+0x220/0x23c Fixes: b4748553f53f ("net: ethernet: mvneta: Fix Serdes configuration for SoCs without comphy") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-03net: ethernet: mvneta: Add back interface mode validationSascha Hauer
commit 41c2b6b4f0f807803bb49f65835d136941a70f85 upstream. When writing the serdes configuration register was moved to mvneta_config_interface() the whole code block was removed from mvneta_port_power_up() in the assumption that its only purpose was to write the serdes configuration register. As mentioned by Russell King its purpose was also to check for valid interface modes early so that later in the driver we do not have to care for unexpected interface modes. Add back the test to let the driver bail out early on unhandled interface modes. Fixes: b4748553f53f ("net: ethernet: mvneta: Fix Serdes configuration for SoCs without comphy") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-03net: mvneta: fix use of state->speedRussell King
commit f2ca673d2cd5df9a76247b670e9ffd4d63682b3f upstream. When support for short preambles was added, it incorrectly keyed its decision off state->speed instead of state->interface. state->speed is not guaranteed to be correct for in-band modes, which can lead to short preambles being unexpectedly disabled. Fix this by keying off the interface mode, which is the only way that mvneta can operate at 2.5Gbps. Fixes: da58a931f248 ("net: mvneta: Add support for 2500Mbps SGMII") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-03net: ethernet: mvneta: Add 2500BaseX support for SoCs without comphySascha Hauer
commit 1a642ca7f38992b086101fe204a1ae3c90ed8016 upstream. The older SoCs like Armada XP support a 2500BaseX mode in the datasheets referred to as DR-SGMII (Double rated SGMII) or HS-SGMII (High Speed SGMII). This is an upclocked 1000BaseX mode, thus PHY_INTERFACE_MODE_2500BASEX is the appropriate mode define for it. adding support for it merely means writing the correct magic value into the MVNETA_SERDES_CFG register. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-08-03net: ethernet: mvneta: Fix Serdes configuration for SoCs without comphySascha Hauer
commit b4748553f53f2971e07d2619f13d461daac0f3bb upstream. The MVNETA_SERDES_CFG register is only available on older SoCs like the Armada XP. On newer SoCs like the Armada 38x the fields are moved to comphy. This patch moves the writes to this register next to the comphy initialization, so that depending on the SoC either comphy or MVNETA_SERDES_CFG is configured. With this we no longer write to the MVNETA_SERDES_CFG on SoCs where it doesn't exist. Suggested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-06-05Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
2020-06-04net: mvpp2: cls: Prevent buffer overflow in mvpp2_ethtool_cls_rule_del()Dan Carpenter
commit 722c0f00d4feea77475a5dc943b53d60824a1e4e upstream. The "info->fs.location" is a u32 that comes from the user via the ethtool_set_rxnfc() function. We need to check for invalid values to prevent a buffer overflow. I copy and pasted this check from the mvpp2_ethtool_cls_rule_ins() function. Fixes: 90b509b39ac9 ("net: mvpp2: cls: Add Classification offload support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-05-25Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-05-21net: mvneta: Fix the case where the last poll did not process all rxJisheng Zhang
commit 065fd83e1be2e1ba0d446a257fd86a3cc7bddb51 upstream. For the case where the last mvneta_poll did not process all RX packets, we need to xor the pp->cause_rx_tx or port->cause_rx_tx before claculating the rx_queue. Fixes: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-05-05Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-05-04net: mvneta: move rx_dropped and rx_errors in per-cpu statsLorenzo Bianconi
commit c35947b8ff8acca33134ee39c31708233765c31a upstream. Move rx_dropped and rx_errors counters in mvneta_pcpu_stats in order to avoid possible races updating statistics Fixes: 562e2f467e71 ("net: mvneta: Improve the buffer allocation method for SWBM") Fixes: dc35a10f68d3 ("net: mvneta: bm: add support for hardware buffer management") Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network unit") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-03-11Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-03-07net: marvell: mvpp2: phylink requires the link interruptRussell King
commit f3f2364ea14d1cf6bf966542f31eadcf178f1577 upstream. phylink requires the MAC to report when its link status changes when operating in inband modes. Failure to report link status changes means that phylink has no idea when the link events happen, which results in either the network interface's carrier remaining up or remaining permanently down. For example, with a fiber module, if the interface is brought up and link is initially established, taking the link down at the far end will cut the optical power. The SFP module's LOS asserts, we deactivate the link, and the network interface reports no carrier. When the far end is brought back up, the SFP module's LOS deasserts, but the MAC may be slower to establish link. If this happens (which in my tests is a certainty) then phylink never hears that the MAC has established link with the far end, and the network interface is stuck reporting no carrier. This means the interface is non-functional. Avoiding the link interrupt when we have phylink is basically not an option, so remove the !port->phylink from the test. Fixes: 4bb043262878 ("net: mvpp2: phylink support") Tested-by: Sven Auhagen <sven.auhagen@voleatech.de> Tested-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-01-30octeontx2-pf: Do not set num_msgs in mbox headerSubbaraya Sundeep
commit 8e7f7faf9d90a84283093e02b90a9e9a12b061ae from git@git.assembla.com:cavium/WindRiver.linux.git A single interrupt line from VF to PF is used by VF to send messages to PF and for replying to UP messages sent by PF. Hence num_msgs in mbox header is cleared explicitly in PF interrupt handler to avoid queuing a work twice for an event. The same num_msgs which was cleared in interrupt handler was set again in work queue handler by mistake. This patch fixes it. Also - clearing interrupt in work queue handlers is not necessary hence removed it. - checking status in message response is not needed hence removed it. Change-Id: I1875d37816b61b4874eea1c7175c63dfea71bcb1 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20142 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Use mutex for mbox lockingSubbaraya Sundeep
commit 46a0ce95e2db7ffd083cd2634b7037f32e27501f from git@git.assembla.com:cavium/WindRiver.linux.git Used mutex instead atomic variables for mailbox lock. Also changed WARN_ON to dev_err. Change-Id: I18e1d3cc013bfc058db47a33ed5d123185d3c5ef Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20141 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Dereference only a valid pointerSubbaraya Sundeep
commit 7aff3a8035f71bfd3675067ea5b79e5ad9b7bd9d from git@git.assembla.com:cavium/WindRiver.linux.git iommu_domain can be NULL hence check for non NULL pointer before dereferencing it. Change-Id: Iff01276a67f35954f1556b731d43339d152e268d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20065 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: update vlan offload rulehariprasad
commit 4ece484b7a0b62a79ab098f75c2a592839d4d7fb from git@git.assembla.com:cavium/WindRiver.linux.git MAC address field in vlan offload rule and interface mac address needs to be same for VLAN offload functionality. So update mac address field in vlan offload rule whenever user changes it. Change-Id: I272ea3b94b7989fd15efd306c27dbae3dddfb2a6 Signed-off-by: hariprasad <hari1219@gmail.com> Reviewed-on: https://sj1git1.cavium.com/19826 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-af: Handle pfvf mac address changeshariprasad
commit d4de909fb7de0de93d168d419ae5621ce0125ea2 from git@git.assembla.com:cavium/WindRiver.linux.git PF set mac address will be persistent across module reload. PF set mac address cannot be overwritten by VF VF set mac address will be preserved until module unload. Change-Id: Ie228a0af9e10ff2fd5e2b0363afd9a24be5f2035 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19827 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Set default RR_QUANTUM for transmit scheduling levelsGeetha sowjanya
commit bbcdd24b2067f23ce553f57bd5153a3e3793b651 from git@git.assembla.com:cavium/WindRiver.linux.git Set RR_QUANTUM value high for transmit levels to prevent negative accumulations of the deficit count. Change-Id: I015ed6cfb27f853d653ebd299492a11bf3990abe Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19885 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-af: Adjust pause frame time and intervalSunil Goutham
commit 721cf946546df138bb6087999d2a693891bfe7d1 from git@git.assembla.com:cavium/WindRiver.linux.git Current pause frame time is too high for a 40G interface. 0xFFFF times 512bits will result in 780us pause time. Reduced pause time config to 0x7FF. Change-Id: I20055d578835926d9027f1a1b32885f91fd52cbe Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19694 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Skip dma map and unmap when IOMMU is bypassedSunil Goutham
commit 94cef32782641d0e0d89a93db273c583d8fb5dd6 from git@git.assembla.com:cavium/WindRiver.linux.git HW takes care of data coherency at LLC level, to save some CPU cycles skip calling dma_map and dma_unmap apis when IOMMU is bypassed. This improves IP forwarding performance by ~5%. These changes are not for upstream. Change-Id: Ie1be6982d62ffe4bbb4434092c0c5ce3575d9339 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19664 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-17octeontx2-pf: Use likely and unlikelySunil Goutham
commit 66a0f365f4618d9528abcdff121a9e57f7bbb1a2 from git@git.assembla.com:cavium/WindRiver.linux.git Add likely and unliley to conditional statements for generation of optimised code by compiler in terms of branching. Change-Id: I7a80fd14999e187732dd8b8b2037544b97bc8800 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19653 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-17octeontx2-pf: Process CQE_TX first and then CQE_RXSunil Goutham
commit 02237bdd58d65c17d5b502bb027290dd7a281bf2 from git@git.assembla.com:cavium/WindRiver.linux.git Process transmitted pkt's CQEs first so that the freed skbs are recycled for received packets. Change-Id: Ia399659851c4b8181619ee212d1c9ee26711efc6 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19652 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-16octeontx2-pf: Discover NIX block address from RVUMSubbaraya Sundeep
commit f5b4312caee99567741fcb75470673d69a771a18 from git@git.assembla.com:cavium/WindRiver.linux.git For platform with two NIX blocks, LF may be allocated from either of NIX blocks. Hence discover the assigned block address from RVUM register. Change-Id: Id34b7ad968c6b91ea41ef833fad6bdebfef61c51 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19496 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-16octeontx2-pf: Remove warning messages in fast pathGeetha sowjanya
commit 8d48b6712f60b9bf29c482c090f3aee1166ac37b from git@git.assembla.com:cavium/WindRiver.linux.git Change-Id: I0bf0176bf6cd32f3a0b4c7963836b848747d626e Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19129 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-af: Add new CGX_CMD to get PHY FEC statisticsFelix Manlunas
commit b1b525868f846e2599dd96ac881d8e483d162c0d from git@git.assembla.com:cavium/WindRiver.linux.git The stats are put in the shared data struct fwdata. A PHY driver indicates that it has FEC stats by setting the flag fwdata.phy.misc.has_fec_stats (for now, only the LIO3 card's 6141 PHY does this; all other PHYs clear that flag). On LIO3, FEC can be enabled at the PHY line-side only, never at the PHY host-side. So for LIO3, the ethtool FEC stats come from the PHY (not from CGX). Besides CGX_CMD_GET_PHY_FEC_STATS, also add CGX_CMD_PRBS and CGX_CMD_DISPLAY_EYE to enum cgx_cmd_id so that Linux's enum list is in sync with ATF's enum list. Change-Id: Ib0cb8e9315b88e3c3f1ddd16cae709f8837d4f1d Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18814 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-af: Undo PTP NPC config in FLRHarman Kalra
commit 56e5f30e794e51e3075a18791198d01cacbfbbc1 from git@git.assembla.com:cavium/WindRiver.linux.git Disable NPC configuration (shift data off by 8 bytes) done for PTP in FLR. Change-Id: I8e6d245ae13601841fbaa03c15da6d9bfc0595d2 Signed-off-by: Harman Kalra <hkalra@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18456 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-pf: Remove ARM64 and LSE_ATOMICS dependencyGeetha sowjanya
commit a9d863bf6de65580c54c2424bdc0d09dce663b67 from git@git.assembla.com:cavium/WindRiver.linux.git Generic arm64 atomic APIs for "ldadd" and "ldeor" instructions can't be used if CONFIG_LSE_ATOMIC is disabled. Hence, using asm instructions to remove dependency on kernel config. Change-Id: I40fd44b6246b3fad7479bc3cd3115c93331f80b6 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18269 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-10octeontx2-af: Fix return value in npc_set_pkindGeetha sowjanya
commit 162b9f43e31611ecfac36820e1b70a2397133624 from git@git.assembla.com:cavium/WindRiver.linux.git Change-Id: I5743e37aa0e3d51602d6658de94c358d2cb6339f Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18164 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit f81d7acae881eabc3aeeb9c47a97ee13ecf5ee6e) Reviewed-on: https://sj1git1.cavium.com/18169 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26net: octeontx2-pf: Don't set the parse mode for LBKsKevin Hao
The LBKs are not allowed to set the parse mode. It will return an error if we try to do so, then cause a failure when opening these ports. Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Allow setting VF mac and vlan only when PF is UPSunil Goutham
commit d91c0634ae5d5e9432f054919a1952dfd91507db from git@git.assembla.com:cavium/WindRiver.linux.git To install NPC MCAM rules to support VF MAC and VF VLAN settings PF needs to know ingress hw channel number. This info is sent to PF by AF in response to NIXLF_ALLOC mbox ie NIXLF init request. So skip 'set vf vlan' and 'set vf mac' if PF interface is not UP. Change-Id: Ib8d0c5c84296aa22090d39038055e769668ac07f Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18079 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use 2048 byte receive buffersSunil Goutham
commit 556600410db1e2490ebf8d46b8f4419b580d8e21 from git@git.assembla.com:cavium/WindRiver.linux.git Use 2048 byte buffers for better last level cache utilization or data distribution across regions. Change-Id: I726bc8919afb8f52bca7da1ff0facbd3cfc378df Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18078 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Advertise lockless transmit capabilitySunil Goutham
commit 39c012db6c348c4f0d02d4a2724607a4e3fe25b4 from git@git.assembla.com:cavium/WindRiver.linux.git Usage of NETIF_F_LLTX is deprecated upstream hence this patch cannot be upstreamed. But still enabling this locally as it improves IP forwarding performance especially when all 24 cores are transmitting pkts. Change-Id: I33a58c0e71d63ee0937ba50c47c5476ba62be094 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18065 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Optimize populating SQE_HDRSunil Goutham
commit fc87b5d941e7357f1da2cd4fab5a71f6e230017d from git@git.assembla.com:cavium/WindRiver.linux.git Fields aura, qidx, pnc, df in SQE_HDR doesn't change for each SQE (or packet). Hence avoid repopulating them for every SQE, this saves few cycles. Change-Id: Ia968853def360aaa360888ec2328c97022e30436 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18066 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Cleanup otx2_nic and hw structsSunil Goutham
commit b17de4c302b0e2faad7bbf4e970538713f35775e from git@git.assembla.com:cavium/WindRiver.linux.git Move HW related settings info fields to otx2_hw struct and cleanup both otx2_nic and otx2_hw structs. Change-Id: Ic142c188b310fe5d4833fe1a85f211deb436a2bc Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18007 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Aggregate multiple boolean fields into common flagsSunil Goutham
commit 97137802696ed80c4125a40ad97f6cd43ec86240 from git@git.assembla.com:cavium/WindRiver.linux.git Cleaned up multiple boolean fields and flags in otx2_nic struct into a single flags field. Change-Id: Ic090c8b06b7cc2c19a0121c913f674330486ad4c Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18006 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Add SDP interface support.Subrahmanyam Nilla
commit 4926267192697d0b61940b42dad702094091c1fe from git@git.assembla.com:cavium/WindRiver.linux.git Right now SDP interface support is limited to single interface/channel and SDP PF(RVU PF) device, No VF support. Change-Id: I4ecce3a42b4537ca34c864ef84bf785482966f81 Signed-off-by: Subrahmanyam Nilla <snilla@marvell.com> Signed-off-by: Venkateshwarlu Nalla <venkatn@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17982 Reviewed-by: Yan Markman <ymarkman@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Alloc only used MSIX vectorsSunil Goutham
commit c94525c3a9b0e992be718aa5dc214bdda0ebd3b8 from git@git.assembla.com:cavium/WindRiver.linux.git Each of the CGX mapped RVU PFVF has 210 MSIX vectors and kernel globally support only 8192 IRQs. So enabling 210 vectors for all PF, their VFs and LBKVFs results in failure of pci_alloc_vectors for some of the devices. Increasing the Linux IRQ count from 8192 has upstream depencency and for reasons unknown resulted in performance regression on Armada silicon. Since netdev drivers are not registering NPA block IRQs, reverse the NPA and NIX MSIX vectors allocation. This way we will end up using vectors less than half of what we are using currently. Vectors allocated are PF_INT + NIX_QINT + NIX_CINT (max queues/cores). Change-Id: I495c2d43caf0f9a8b12407ef44cfbe13bd01c25e Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17958 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use napi_complete_done instead of napi_completeSunil Goutham
commit b1eb5ae22500bf8984c4fe4facd0a55fc659a819 from git@git.assembla.com:cavium/WindRiver.linux.git Use napi_complete_done to allow for the use of gro_flush_timeout. Change-Id: Ic9456cbcd147c5613d5aa99301a80084ab23dd57 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17957 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use napi_get_frags instead of build_skbSunil Goutham
commit 2e161e8b861ab07e73257e6c0abf29ffb042ada8 from git@git.assembla.com:cavium/WindRiver.linux.git For GRO'ble packets napi_get_frags helps in recycling SKBs instead of allocating new SKB for every packet. This improves performance of GRO'ble frames but effects IP forwarding performance. Change-Id: I191194cb5feefb1e617a4c7fa152f0e325d9aa1a Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17956 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix CQE cleanup done while teardownSunil Goutham
commit e6c9a391e46edc478b6ac0b7bf57493a969979f0 from git@git.assembla.com:cavium/WindRiver.linux.git Current cleanup is done using napi structs which when used in non-napi context leads to issues. This patch fixes this issue. Change-Id: I3b13e5c4ec54e4a6a4f902e28170367f88a9ef67 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17955 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: NAPI handler cleanupSunil Goutham
commit d8a3a2d822c226650d7f362c291d3c4ad0a7031e from git@git.assembla.com:cavium/WindRiver.linux.git Major changes done - Segregate Rx and Tx CQ handlers - Removed costly CQ_OP_STATUS reads, instead check cqe_type in cqe_hdr to determine valid CQE. Change-Id: I14bfcf2dae39178681464b10174fb269a89c46a0 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17954 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Support to enable EDSA/Higig2 pkts parsinghariprasad
commit e768cc7824fd22df72cdef19f517697408bd33d3 from git@git.assembla.com:cavium/WindRiver.linux.git When switch headers like EDSA, Higig2 etc are present in ingress or egress pkts the pkt parsing done by NPC needs to take additional headers into account. KPU profile handles these using specific PKINDs (the iKPU index) to start parsing pkts differently. This patch enables user to configure these PKINDs into HW for proper pkt parsing. Patch also handles changes to max frame size due to additional headers in pkt. higig2: ethtool --set-priv-flags eth0 higig2 on/off edsa: ethtool --set-priv-flags eth0 edsa on/off Change-Id: If27c198a555b480434a5d56e15f0f7cff3800144 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17912 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Drop packets size more than configured FRSGeetha sowjanya
commit ec5575a4f4505c09b75c2d40b71371ef88c9be15 from git@git.assembla.com:cavium/WindRiver.linux.git Drop packets with length more than configured FRS to avoid SQ Meta-descriptor error. This patch also include some cleanup changes. Change-Id: I4c28134e004151094de125189f0f904d6a29a7a2 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17865 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit f910cf67294b5f9ff3e902154e51afb218219997) Reviewed-on: https://sj1git1.cavium.com/17873 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: add default ldata ext for higig2Kiran Kumar K
commit 51edab760bd32c81bd807e61061b92cf105617e4 from git@git.assembla.com:cavium/WindRiver.linux.git Adding the default ldata extraction profile for higig2 header. Ingress side we will extract classification and vid and for egress side we will extract classification. These fields has been placed in place of DMAC. Change-Id: Id439af938b359ded470a3690e2d90dfa7a39c0a0 Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17480 Reviewed-by: Subbaraya Sundeep Bhatta <Sundeep.Bhatta@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-26 12:29:50 +0000