aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/marvell/octeontx2
AgeCommit message (Collapse)Author
2020-09-21Merge branch 'v5.2/standard/base' into v5.2/standard/cn96xxBruce Ashfield
2020-09-17octeontx2-af: change (struct qmem)->entry_sz from u8 to u16Eric Dumazet
commit 393415203f5c916b5907e0a7c89f4c2c5a9c5505 upstream. We need to increase TSO_HEADER_SIZE from 128 to 256. Since otx2_sq_init() calls qmem_alloc() with TSO_HEADER_SIZE, we need to change (struct qmem)->entry_sz to avoid truncation to 0. Fixes: 7a37245ef23f ("octeontx2-af: NPA block admin queue init") Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2020-01-30octeontx2-pf: Do not set num_msgs in mbox headerSubbaraya Sundeep
commit 8e7f7faf9d90a84283093e02b90a9e9a12b061ae from git@git.assembla.com:cavium/WindRiver.linux.git A single interrupt line from VF to PF is used by VF to send messages to PF and for replying to UP messages sent by PF. Hence num_msgs in mbox header is cleared explicitly in PF interrupt handler to avoid queuing a work twice for an event. The same num_msgs which was cleared in interrupt handler was set again in work queue handler by mistake. This patch fixes it. Also - clearing interrupt in work queue handlers is not necessary hence removed it. - checking status in message response is not needed hence removed it. Change-Id: I1875d37816b61b4874eea1c7175c63dfea71bcb1 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20142 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Use mutex for mbox lockingSubbaraya Sundeep
commit 46a0ce95e2db7ffd083cd2634b7037f32e27501f from git@git.assembla.com:cavium/WindRiver.linux.git Used mutex instead atomic variables for mailbox lock. Also changed WARN_ON to dev_err. Change-Id: I18e1d3cc013bfc058db47a33ed5d123185d3c5ef Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20141 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Dereference only a valid pointerSubbaraya Sundeep
commit 7aff3a8035f71bfd3675067ea5b79e5ad9b7bd9d from git@git.assembla.com:cavium/WindRiver.linux.git iommu_domain can be NULL hence check for non NULL pointer before dereferencing it. Change-Id: Iff01276a67f35954f1556b731d43339d152e268d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20065 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: update vlan offload rulehariprasad
commit 4ece484b7a0b62a79ab098f75c2a592839d4d7fb from git@git.assembla.com:cavium/WindRiver.linux.git MAC address field in vlan offload rule and interface mac address needs to be same for VLAN offload functionality. So update mac address field in vlan offload rule whenever user changes it. Change-Id: I272ea3b94b7989fd15efd306c27dbae3dddfb2a6 Signed-off-by: hariprasad <hari1219@gmail.com> Reviewed-on: https://sj1git1.cavium.com/19826 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-af: Handle pfvf mac address changeshariprasad
commit d4de909fb7de0de93d168d419ae5621ce0125ea2 from git@git.assembla.com:cavium/WindRiver.linux.git PF set mac address will be persistent across module reload. PF set mac address cannot be overwritten by VF VF set mac address will be preserved until module unload. Change-Id: Ie228a0af9e10ff2fd5e2b0363afd9a24be5f2035 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19827 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Set default RR_QUANTUM for transmit scheduling levelsGeetha sowjanya
commit bbcdd24b2067f23ce553f57bd5153a3e3793b651 from git@git.assembla.com:cavium/WindRiver.linux.git Set RR_QUANTUM value high for transmit levels to prevent negative accumulations of the deficit count. Change-Id: I015ed6cfb27f853d653ebd299492a11bf3990abe Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19885 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-af: Adjust pause frame time and intervalSunil Goutham
commit 721cf946546df138bb6087999d2a693891bfe7d1 from git@git.assembla.com:cavium/WindRiver.linux.git Current pause frame time is too high for a 40G interface. 0xFFFF times 512bits will result in 780us pause time. Reduced pause time config to 0x7FF. Change-Id: I20055d578835926d9027f1a1b32885f91fd52cbe Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19694 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-01-30octeontx2-pf: Skip dma map and unmap when IOMMU is bypassedSunil Goutham
commit 94cef32782641d0e0d89a93db273c583d8fb5dd6 from git@git.assembla.com:cavium/WindRiver.linux.git HW takes care of data coherency at LLC level, to save some CPU cycles skip calling dma_map and dma_unmap apis when IOMMU is bypassed. This improves IP forwarding performance by ~5%. These changes are not for upstream. Change-Id: Ie1be6982d62ffe4bbb4434092c0c5ce3575d9339 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19664 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-17octeontx2-pf: Use likely and unlikelySunil Goutham
commit 66a0f365f4618d9528abcdff121a9e57f7bbb1a2 from git@git.assembla.com:cavium/WindRiver.linux.git Add likely and unliley to conditional statements for generation of optimised code by compiler in terms of branching. Change-Id: I7a80fd14999e187732dd8b8b2037544b97bc8800 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19653 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-17octeontx2-pf: Process CQE_TX first and then CQE_RXSunil Goutham
commit 02237bdd58d65c17d5b502bb027290dd7a281bf2 from git@git.assembla.com:cavium/WindRiver.linux.git Process transmitted pkt's CQEs first so that the freed skbs are recycled for received packets. Change-Id: Ia399659851c4b8181619ee212d1c9ee26711efc6 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19652 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-16octeontx2-pf: Discover NIX block address from RVUMSubbaraya Sundeep
commit f5b4312caee99567741fcb75470673d69a771a18 from git@git.assembla.com:cavium/WindRiver.linux.git For platform with two NIX blocks, LF may be allocated from either of NIX blocks. Hence discover the assigned block address from RVUM register. Change-Id: Id34b7ad968c6b91ea41ef833fad6bdebfef61c51 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19496 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-16octeontx2-pf: Remove warning messages in fast pathGeetha sowjanya
commit 8d48b6712f60b9bf29c482c090f3aee1166ac37b from git@git.assembla.com:cavium/WindRiver.linux.git Change-Id: I0bf0176bf6cd32f3a0b4c7963836b848747d626e Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/19129 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-af: Add new CGX_CMD to get PHY FEC statisticsFelix Manlunas
commit b1b525868f846e2599dd96ac881d8e483d162c0d from git@git.assembla.com:cavium/WindRiver.linux.git The stats are put in the shared data struct fwdata. A PHY driver indicates that it has FEC stats by setting the flag fwdata.phy.misc.has_fec_stats (for now, only the LIO3 card's 6141 PHY does this; all other PHYs clear that flag). On LIO3, FEC can be enabled at the PHY line-side only, never at the PHY host-side. So for LIO3, the ethtool FEC stats come from the PHY (not from CGX). Besides CGX_CMD_GET_PHY_FEC_STATS, also add CGX_CMD_PRBS and CGX_CMD_DISPLAY_EYE to enum cgx_cmd_id so that Linux's enum list is in sync with ATF's enum list. Change-Id: Ib0cb8e9315b88e3c3f1ddd16cae709f8837d4f1d Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18814 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-af: Undo PTP NPC config in FLRHarman Kalra
commit 56e5f30e794e51e3075a18791198d01cacbfbbc1 from git@git.assembla.com:cavium/WindRiver.linux.git Disable NPC configuration (shift data off by 8 bytes) done for PTP in FLR. Change-Id: I8e6d245ae13601841fbaa03c15da6d9bfc0595d2 Signed-off-by: Harman Kalra <hkalra@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18456 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-11octeontx2-pf: Remove ARM64 and LSE_ATOMICS dependencyGeetha sowjanya
commit a9d863bf6de65580c54c2424bdc0d09dce663b67 from git@git.assembla.com:cavium/WindRiver.linux.git Generic arm64 atomic APIs for "ldadd" and "ldeor" instructions can't be used if CONFIG_LSE_ATOMIC is disabled. Hence, using asm instructions to remove dependency on kernel config. Change-Id: I40fd44b6246b3fad7479bc3cd3115c93331f80b6 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18269 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-12-10octeontx2-af: Fix return value in npc_set_pkindGeetha sowjanya
commit 162b9f43e31611ecfac36820e1b70a2397133624 from git@git.assembla.com:cavium/WindRiver.linux.git Change-Id: I5743e37aa0e3d51602d6658de94c358d2cb6339f Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18164 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit f81d7acae881eabc3aeeb9c47a97ee13ecf5ee6e) Reviewed-on: https://sj1git1.cavium.com/18169 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26net: octeontx2-pf: Don't set the parse mode for LBKsKevin Hao
The LBKs are not allowed to set the parse mode. It will return an error if we try to do so, then cause a failure when opening these ports. Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Allow setting VF mac and vlan only when PF is UPSunil Goutham
commit d91c0634ae5d5e9432f054919a1952dfd91507db from git@git.assembla.com:cavium/WindRiver.linux.git To install NPC MCAM rules to support VF MAC and VF VLAN settings PF needs to know ingress hw channel number. This info is sent to PF by AF in response to NIXLF_ALLOC mbox ie NIXLF init request. So skip 'set vf vlan' and 'set vf mac' if PF interface is not UP. Change-Id: Ib8d0c5c84296aa22090d39038055e769668ac07f Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18079 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use 2048 byte receive buffersSunil Goutham
commit 556600410db1e2490ebf8d46b8f4419b580d8e21 from git@git.assembla.com:cavium/WindRiver.linux.git Use 2048 byte buffers for better last level cache utilization or data distribution across regions. Change-Id: I726bc8919afb8f52bca7da1ff0facbd3cfc378df Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18078 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Advertise lockless transmit capabilitySunil Goutham
commit 39c012db6c348c4f0d02d4a2724607a4e3fe25b4 from git@git.assembla.com:cavium/WindRiver.linux.git Usage of NETIF_F_LLTX is deprecated upstream hence this patch cannot be upstreamed. But still enabling this locally as it improves IP forwarding performance especially when all 24 cores are transmitting pkts. Change-Id: I33a58c0e71d63ee0937ba50c47c5476ba62be094 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18065 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Optimize populating SQE_HDRSunil Goutham
commit fc87b5d941e7357f1da2cd4fab5a71f6e230017d from git@git.assembla.com:cavium/WindRiver.linux.git Fields aura, qidx, pnc, df in SQE_HDR doesn't change for each SQE (or packet). Hence avoid repopulating them for every SQE, this saves few cycles. Change-Id: Ia968853def360aaa360888ec2328c97022e30436 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18066 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Cleanup otx2_nic and hw structsSunil Goutham
commit b17de4c302b0e2faad7bbf4e970538713f35775e from git@git.assembla.com:cavium/WindRiver.linux.git Move HW related settings info fields to otx2_hw struct and cleanup both otx2_nic and otx2_hw structs. Change-Id: Ic142c188b310fe5d4833fe1a85f211deb436a2bc Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18007 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Aggregate multiple boolean fields into common flagsSunil Goutham
commit 97137802696ed80c4125a40ad97f6cd43ec86240 from git@git.assembla.com:cavium/WindRiver.linux.git Cleaned up multiple boolean fields and flags in otx2_nic struct into a single flags field. Change-Id: Ic090c8b06b7cc2c19a0121c913f674330486ad4c Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/18006 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Add SDP interface support.Subrahmanyam Nilla
commit 4926267192697d0b61940b42dad702094091c1fe from git@git.assembla.com:cavium/WindRiver.linux.git Right now SDP interface support is limited to single interface/channel and SDP PF(RVU PF) device, No VF support. Change-Id: I4ecce3a42b4537ca34c864ef84bf785482966f81 Signed-off-by: Subrahmanyam Nilla <snilla@marvell.com> Signed-off-by: Venkateshwarlu Nalla <venkatn@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17982 Reviewed-by: Yan Markman <ymarkman@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Alloc only used MSIX vectorsSunil Goutham
commit c94525c3a9b0e992be718aa5dc214bdda0ebd3b8 from git@git.assembla.com:cavium/WindRiver.linux.git Each of the CGX mapped RVU PFVF has 210 MSIX vectors and kernel globally support only 8192 IRQs. So enabling 210 vectors for all PF, their VFs and LBKVFs results in failure of pci_alloc_vectors for some of the devices. Increasing the Linux IRQ count from 8192 has upstream depencency and for reasons unknown resulted in performance regression on Armada silicon. Since netdev drivers are not registering NPA block IRQs, reverse the NPA and NIX MSIX vectors allocation. This way we will end up using vectors less than half of what we are using currently. Vectors allocated are PF_INT + NIX_QINT + NIX_CINT (max queues/cores). Change-Id: I495c2d43caf0f9a8b12407ef44cfbe13bd01c25e Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17958 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use napi_complete_done instead of napi_completeSunil Goutham
commit b1eb5ae22500bf8984c4fe4facd0a55fc659a819 from git@git.assembla.com:cavium/WindRiver.linux.git Use napi_complete_done to allow for the use of gro_flush_timeout. Change-Id: Ic9456cbcd147c5613d5aa99301a80084ab23dd57 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17957 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use napi_get_frags instead of build_skbSunil Goutham
commit 2e161e8b861ab07e73257e6c0abf29ffb042ada8 from git@git.assembla.com:cavium/WindRiver.linux.git For GRO'ble packets napi_get_frags helps in recycling SKBs instead of allocating new SKB for every packet. This improves performance of GRO'ble frames but effects IP forwarding performance. Change-Id: I191194cb5feefb1e617a4c7fa152f0e325d9aa1a Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17956 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix CQE cleanup done while teardownSunil Goutham
commit e6c9a391e46edc478b6ac0b7bf57493a969979f0 from git@git.assembla.com:cavium/WindRiver.linux.git Current cleanup is done using napi structs which when used in non-napi context leads to issues. This patch fixes this issue. Change-Id: I3b13e5c4ec54e4a6a4f902e28170367f88a9ef67 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17955 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: NAPI handler cleanupSunil Goutham
commit d8a3a2d822c226650d7f362c291d3c4ad0a7031e from git@git.assembla.com:cavium/WindRiver.linux.git Major changes done - Segregate Rx and Tx CQ handlers - Removed costly CQ_OP_STATUS reads, instead check cqe_type in cqe_hdr to determine valid CQE. Change-Id: I14bfcf2dae39178681464b10174fb269a89c46a0 Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17954 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Support to enable EDSA/Higig2 pkts parsinghariprasad
commit e768cc7824fd22df72cdef19f517697408bd33d3 from git@git.assembla.com:cavium/WindRiver.linux.git When switch headers like EDSA, Higig2 etc are present in ingress or egress pkts the pkt parsing done by NPC needs to take additional headers into account. KPU profile handles these using specific PKINDs (the iKPU index) to start parsing pkts differently. This patch enables user to configure these PKINDs into HW for proper pkt parsing. Patch also handles changes to max frame size due to additional headers in pkt. higig2: ethtool --set-priv-flags eth0 higig2 on/off edsa: ethtool --set-priv-flags eth0 edsa on/off Change-Id: If27c198a555b480434a5d56e15f0f7cff3800144 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17912 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Drop packets size more than configured FRSGeetha sowjanya
commit ec5575a4f4505c09b75c2d40b71371ef88c9be15 from git@git.assembla.com:cavium/WindRiver.linux.git Drop packets with length more than configured FRS to avoid SQ Meta-descriptor error. This patch also include some cleanup changes. Change-Id: I4c28134e004151094de125189f0f904d6a29a7a2 Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17865 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit f910cf67294b5f9ff3e902154e51afb218219997) Reviewed-on: https://sj1git1.cavium.com/17873 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: add default ldata ext for higig2Kiran Kumar K
commit 51edab760bd32c81bd807e61061b92cf105617e4 from git@git.assembla.com:cavium/WindRiver.linux.git Adding the default ldata extraction profile for higig2 header. Ingress side we will extract classification and vid and for egress side we will extract classification. These fields has been placed in place of DMAC. Change-Id: Id439af938b359ded470a3690e2d90dfa7a39c0a0 Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17480 Reviewed-by: Subbaraya Sundeep Bhatta <Sundeep.Bhatta@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: kpu profile add support for HIGIG2 protocolHao Zheng
commit dd6d25e1cb573750dedd0d1b04e9cd0b6418cd36 from git@git.assembla.com:cavium/WindRiver.linux.git Add support for HIGIG2 protocol header to the kpu parser profile Add a NPC_LT_LA_HIGIG2_ETHER for a combined header of HIGIG2 and Ethernet. Add a NPC_LT_LA_IH_NIX_HIGIG2_ETHER for a combined header of nix_ih, HIGIG2 and Ethernet. Also add 2 upper flags in LA to indicate the presence of nix_ih and HIGIG2. Change-Id: I652ed86ab1f06f5b7f90ac4e985e1c0c854108b8 Signed-off-by: Hao Zheng <haoz@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17841 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Add LIO3 link modes to ethtool's list of supported modesFelix Manlunas
commit a108847efc4ad4a07bb7f5a2612391047e979620 from git@git.assembla.com:cavium/WindRiver.linux.git For the PHY host-side, LIO3 uses the Marvell proprietary PCS types 25GBASE-R2 and 50GBASE-R4; each is combined (at the PHY line-side) with its counterpart (25G/50G Ethernet Consortium) standard PCS type (25GBASE-R or 50GBASE-R2). ethtool is not aware of and does not support Marvell proprietary PCS types; it only knows about standard PCS types. So the PF driver must pass (to ethtool) information about LIO3's PHY line-side (not PHY host-side). To that end, replace the entries of the cgx_link_mode[] lookup table that correspond to the proprietary PCS types with their standard counterparts. Also, set the bits of the macro OTX2_ETHTOOL_SUPPORTED_MODES that correspond to the proprietary modes/types. Change-Id: I993906364747abb4f75ae5ce235bf6af96ee70d0 Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17825 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit c0b60c39f136e42619e9a8602b52e299af1359d1) Reviewed-on: https://sj1git1.cavium.com/17834 [Kevin: Just some minor context mods in order to port to linux-yocto] Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: notify VF about ptp eventHarman Kalra
commit 1f56892993fb7d9b4aa13ed8481e3422e3d87ab1 from git@git.assembla.com:cavium/WindRiver.linux.git In case of PTP enable/disable event, PF should inform its VFs about the event. So that VFs can adjust the shifted data offset (viz 8 bytes on PTP enable). Change-Id: I83d45441ee18c53bad3b68249c32cdc273cf4fc9 Signed-off-by: Harman Kalra <hkalra@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17618 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Increase mbox response timeout to 2 secondsFelix Manlunas
commit 3d41081109f29fdf84517b3cd1220852f783b382 from git@git.assembla.com:cavium/WindRiver.linux.git It used to be that the intended 1 second mbox response timeout was not very precise such that the effective timeout was longer than 1 second. Recently code was checked in to make the timeout very precise. It turns out that the old, imprecise, longer-than-1-second timeout was beneficial. Now that it's been replaced with a precise 1-second timeout, we sometimes see these alarming error messages from ethtool: Cannot set new settings: Input/output error Cannot set private flags: Input/output error These turn out to be false alarms because the operations (of changing Ethernet speed or setting private flags) actually take effect. One second is not enough time for ATF to detect the arrival of a CGX_CMD, to execute the command, and to send back a response. Increase the timeout to 2 seconds for ample safety margin. Change-Id: Ia663fdf55a7a1417fc2d8b9ee751cab0903a7710 Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17678 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit b842f3df534a85e70811b4490900a10d17f46f99) Reviewed-on: https://sj1git1.cavium.com/17824 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Use BLKTYPE in register macrosSubbaraya Sundeep
commit 671aef6d85d317e805ac179c3d6d2983835e9ea1 from git@git.assembla.com:cavium/WindRiver.linux.git Use BLKTYPE instead of BLKADDR in register offset macros so that NIX1 block registers can also be accessed when required. Change-Id: I4f32885fe2fa28beb3483f84c3b13d4eb5818c04 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17664 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Support for parsing pkts with switch headershariprasad
commit 72df259bd2f894a62c3c78e97883afe90940243c from git@git.assembla.com:cavium/WindRiver.linux.git Switch headers are designed to support better flow control and loadbalancing etc. When switch headers like EDSA, Higig2 etc are present in ingress or egress pkts default iKPU index (or PKIND) used by NPC to parse pkts will not work as there are additional headers appended to the pkt. Hence a separate Pkind is chosen on Rx and/or Tx sides to tell to KPU to parse the pkts accordingly. Changes to NPC KPU parse profile to parse headers using these iKPU indices will be pushed as a separate patch Change-Id: I1796bafadb507a528d41f96376bf44eb33cc4bb3 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17520 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix wrong info in ethtool's list of supported link modesFelix Manlunas
commit 5fe1527404347eba09db0d56b92c5cbf0a2f3092 from git@git.assembla.com:cavium/WindRiver.linux.git In otx2_get_link_mode_info(), the signed integer literal "1" is left- shifted by a value obtained by the table lookup "cgx_link_mode[bit_position]". The result is then implicitly promoted from signed int to u64 before it gets bitwise-ORed and assigned to "ethtool_link_mode" (whose type is u64). This is problematic if the result of the table lookup (which is used as the number of bit positions to left shift) is greater than or equal to 31 (one less than the bitwidth of an int). Such a situation will lead to a wrong value for "ethtool_link_mode", causing ethtool to show wrong or incomplete information in the list of supported link modes. Fix it by adding the "ULL" suffix to "1". Change-Id: I411befd4ad23df2566bf5e9cd6141faeeb53a26c Signed-off-by: Felix Manlunas <fmanlunas@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17524 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit 8b1d4774140e9b1ff99a49e2b6ab8b610631c2e9) Reviewed-on: https://sj1git1.cavium.com/17537 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Fix clearing SQ/CQ queue interruptGeetha sowjanya
commit 751d5a0b04b7af458779149ae33cf44071e9f905 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes cleaning SQ/CQ queue interrupt bits and LBK VF interface state after changing Queue length or number of TX/RX queues using ethtool. Change-Id: Ic0b98cc4eee22ce32c2247a8c1ffc89c3dbea6aa Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16691 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: Reduce mbox wait response time.Geetha sowjanya
commit 9a12d900323a132d38f0f238a971c31458ac93cb from git@git.assembla.com:cavium/WindRiver.linux.git msleep(1) in "mbox_wait_rsp()" often sleep longer i.e, ~10m. Replacing with usleep_range() as it builts on hrtimer, the wakeup will be very precise. Change-Id: I8c674f507a7d36422b1f7f73b344e25ce53a6eef Signed-off-by: Geetha sowjanya <gakula@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16690 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af: dont force enable default unicast entryhariprasad
commit debcb5884a13363a4d387ffa7cac2dd56f5ac568 from git@git.assembla.com:cavium/WindRiver.linux.git Functions which install default mcam rules like unicast, enable entries as well. This patch modifies that behavior to enable only when they were enabled before. This simplifies logic such that traffic is received only after rvu_mbox_handler_nix_lf_start_rx is called. Change-Id: I936097892c63f5210dd62e4328a2b89db45fc16f Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17493 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-pf: Simplify ndo vf mac and vlanhariprasad
commit 68c4f101435f82b4071116ff7457c51ffcdd90a8 from git@git.assembla.com:cavium/WindRiver.linux.git Irrespective of vf interface state always send request to AF. Change-Id: I0cae60a18cef19cd95990c4a17ec61429fc2ce2e Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17412 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-26octeontx2-af : handle rvu pfvf mac addresshariprasad
commit a58cab5aa7d440e7e9608c55a4814e862e93a55d from git@git.assembla.com:cavium/WindRiver.linux.git Update rvu pfvf mac address in below cases * when fwdata has invalid mac * pf/vf request change in mac address Change-Id: I7d9da0e5aa810175c1aa6438c787e9f525c66942 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17411 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-11-25octeontx2-af: Get MSIXTR_BASE from fw_dataRakesh Babu
commit b58685bf513cb05f282dcfb7817664ac711ee4c0 from git@git.assembla.com:cavium/WindRiver.linux.git Get MSIX base address from firmware via fwdata structure instead of from CSR as the later will cause issue when kernel crashes and Kexec/Kdump loads secondary kernel and AF driver in the secondary kernel reads IOVA written by primary. Change-Id: I5a54638e2909e208537c68d4725f8f159201fc9d Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/17057 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: reserve top LD/LTYPEs for custom KPUStanislaw Kardach
commit 367da0d198068dd4b1310beb78ec4eb62729f7af from git@git.assembla.com:cavium/WindRiver.linux.git OCTEONTX2 NPC KPU parser configuration can be adapted to parse custom packet frames. Such configuration is called a "KPU profile". It defines both the KPU state machine as well as the LD/LTYPE values used in MCAM classification and visible in packet metadata. For performance and interoperability reasons it is best to leave a common set of LD/LTYPE flags static for all users of the HW. This commit reserves top 2 LTYPE values in each LD to allow custom creating profiles with custom protocols that would be interoperable with standard profile users. Change-Id: I31f907850da114c44c25db6b1190f6deddf7471a Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16546 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: update address of global CGX RX_STATShariprasad
commit 73be0de715d6027c9e32fb91c659e7caae032ec5 from git@git.assembla.com:cavium/WindRiver.linux.git Update address for global CGX RX_STATS by passing proper lmac value. Change-Id: I9a00411b993a11a6c7328af9b519aa809f659444 Signed-off-by: hariprasad <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16569 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2019-10-31octeontx2-af: Fix default profile loading checksSubbaraya Sundeep
commit b86183aa6f19548eab924c7155f4a35005965798 from git@git.assembla.com:cavium/WindRiver.linux.git Keysize of default profile is vaildated using a variable which gets initialized later. Hence get key size from register for the validation. Change-Id: Ib44ebfc1c9c9c322ebc0e0228fe0b613333214d6 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/16520 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-27 02:57:03 +0000