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path: root/drivers/irqchip/irq-gic-v3-its.c
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2014-12-13irqchip: gicv3-its: Fix ITT allocationMarc Zyngier
When issuing a MAPD command, one of the parameters passed to the ITS is the number of EventID bits used to index the per-device Interrupt Translation Table (ITT). Crucially, this is the number of bits *minus one*. This has two consequences: - The size of the ITT has to be a strict power of two, no matter how many different events the device is actually going to generate. - It is impossible to express an ITT with a single entry, as you would have to tell the ITS to "use zero bit from the EventID", and that clashes with "minus one" above. Fix this by allocating the ITT with the number of vectors rounded up to the next power of two, with a minimum of two entries. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Yun Wu (Abel) <wuyun.wu@huawei.com> Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-12-13irqchip: gicv3-its: Move some alloc/free code to activate/deactivateMarc Zyngier
The ITS code could do a bit less in the alloc/free paths, and a bit more in the activate/deactivate methods, giving a better separation between software allocation and HW programing. Suggested-by: Wuyun Wu (Abel) <wuyun.wu@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Yun Wu (Abel) <wuyun.wu@huawei.com> Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-12-13irqchip: gicv3-its: Fix domain free in multi-MSI caseMarc Zyngier
Fix stupid thinko on the path freeing the interrupts, where only the first interrupt would get reset, and none of the others. This should only affect multi-MSI allocations. Reported-by: Wuyun Wu (Abel) <wuyun.wu@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-11-26irqchip: GICv3: ITS: DT probing and initializationMarc Zyngier
Add the code that probes the ITS from the device tree, and initialize it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-11-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: MSI supportMarc Zyngier
Now, the bit of code that allow us to use the ITS as a MSI controller. Both MSI and MSI-X are supported. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-10-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: device allocation and configurationMarc Zyngier
The ITS has a notion of "device" that can write to it in order to generate an interrupt. Conversly, the driver maintains a per-ITS list of devices, together with their configuration information, and uses this to configure the HW. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-9-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: tables allocatorsMarc Zyngier
The interrupt translation is driven by a set of tables (device, ITT, and collection) to be in the end delivered to a CPU. Also, the redistributors rely on a couple of tables (configuration, and pending) to deliver the interrupts to the CPUs. This patch adds the required allocators for these tables. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-8-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: LPI allocatorMarc Zyngier
LPIs are the type of interrupts that are used by the ITS. Given the size of the namespace (anywhere between 16 and 32bit), interrupt IDs are allocated in chunks of 32. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-7-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: irqchip implementationMarc Zyngier
The usual methods that are used to present an irqchip to the rest of the kernel Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-6-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS command queueMarc Zyngier
The ITS is configured through a number commands that the driver issues to the HW using a memory-based circular buffer. This patch implements the subset of commands that are required for Linux. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-5-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>