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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
AgeCommit message (Expand)Author
2018-07-19Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva
2018-07-02drm/i915: Use drm_plane_mask() & co.Ville Syrjälä
2018-06-21drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak
2018-06-21drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHzImre Deak
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare
2018-05-07drm/i915/icl: compute the MG PLL registersPaulo Zanoni
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) HDMI registersPaulo Zanoni
2018-05-07drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni
2018-03-27drm/i915: reorder dpll_info membersLucas De Marchi
2018-03-27drm/i915: use flags from dpll_info embedded in intel_shared_dpllLucas De Marchi
2018-03-27drm/i915: use id from intel_shared_dpll.infoLucas De Marchi
2018-03-27drm/i915: use name from intel_shared_dpll.infoLucas De Marchi
2018-03-27drm/i915: use funcs from intel_shared_dpll.infoLucas De Marchi
2018-03-27drm/i915: add dpll_info inside intel_shared_dpllLucas De Marchi
2018-03-27drm/i915: move dpll_info to headerLucas De Marchi
2017-11-16drm/i915/cnl: Simplify dco_fraction calculation.Rodrigo Vivi
2017-11-16drm/i915/cnl: Don't blindly replace qdiv.Rodrigo Vivi
2017-11-16drm/i915/cnl: Fix wrpll math for higher freqs.Rodrigo Vivi
2017-11-16drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.Rodrigo Vivi
2017-11-16drm/i915/cnl: Remove useless conversion.Rodrigo Vivi
2017-11-16drm/i915/cnl: Remove spurious central_freq.Rodrigo Vivi
2017-11-09drm/i915: Replace dig_port->port with encoder port for BXT DPLL selectionVille Syrjälä
2017-10-27drm/i915: Start using output_types for DPLL selectionVille Syrjälä
2017-10-25drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä
2017-10-16drm/i915/cnl: Fix PLL initialization for HDMI.Rodrigo Vivi
2017-08-11drm/i915/cnl: Dump the right pll registers when dumping pipe config.Rodrigo Vivi
2017-06-15drm/i915/cnl: make function cnl_ddi_dp_set_dpll_hw_state staticColin Ian King
2017-06-12drm/i915/cnl: Enable wrpll computation for CNLKahola, Mika
2017-06-12drm/i915/cnl: Initialize PLLsRodrigo Vivi
2017-02-10drm/i915: Remove unused function intel_ddi_get_link_dpll()Ander Conselvan de Oliveira
2017-02-03drm/i915/bxt: Add MST support when do DPLL calculationLee, Shawn C
2017-01-24drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.Rodrigo Vivi
2017-01-02drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.cAnder Conselvan de Oliveira
2016-12-30drm/i915: Add dpll entrypoint for dumping hw stateAnder Conselvan de Oliveira
2016-12-30drm/i915: Update kerneldoc for intel_dpll_mgr.cAnder Conselvan de Oliveira
2016-12-30drm/i915: Rename intel_shared_dpll->mode_set() to prepare()Ander Conselvan de Oliveira
2016-12-30drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_stateAnder Conselvan de Oliveira
2016-12-30drm/i915: Rename intel_shared_dpll_commit() to _swap_state()Ander Conselvan de Oliveira
2016-12-30drm/i915: Introduce intel_release_shared_dpll()Ander Conselvan de Oliveira
2016-12-02drm/i915/glk: Update Port PLL enable sequence for GeminilkaeMadhav Chauhan
2016-12-02drm/i915/glk: Set DCC delay range 2 in PLL enable sequenceAnder Conselvan de Oliveira
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira
2016-11-17drm/i915: Assorted INTEL_INFO(dev) cleanupsTvrtko Ursulin
2016-10-28drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira
2016-10-14drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin
2016-10-14drm/i915: Make IS_KABYLAKE only take dev_privTvrtko Ursulin
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