summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)Author
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau
2015-05-20drm/i915/bxt: Move around lane stagger calculationVandana Kannan
2015-05-20drm/i915/bxt: Port PLL programming BUNVandana Kannan
2015-05-20drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira
2015-05-08drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau
2015-05-08drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira
2015-05-08drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal
2015-05-08drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau
2015-04-30drm/i915: fix intel_prepare_ddiImre Deak
2015-04-30drm/i915: factor out ddi_get_encoder_portImre Deak
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan
2015-04-16drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau
2015-04-16drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau
2015-04-16drm/i915/bxt: Determine programmed frequencySatheeshakrishna M
2015-04-16drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M
2015-04-16drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M
2015-04-16drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M
2015-04-16drm/i915/skl: Add back HDMI translation tableSonika Jindal
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter
2015-04-13drm/i915: Allocate connector state together with the connectorsAnder Conselvan de Oliveira
2015-04-09drm/i915/bxt: Increase DDI buf idle timeoutVandana Kannan
2015-03-31drm/i915: Convert the ddi cdclk code to get_display_clock_speedVille Syrjälä
2015-03-26drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder()Ander Conselvan de Oliveira
2015-03-17drm/i915/skl: Add support for edp 1.4 intermediate frequenciesSonika Jindal
2015-03-17drm/i915/skl: Only use the 800mV+2bB HDMI translation entryDamien Lespiau
2015-02-25drm/i915/skl: Add support for edp1.4 low vswingSonika Jindal
2015-01-30drm/i915: Use pipe_config's cpu_transcoder for reading encoder hw stateAnder Conselvan de Oliveira
2015-01-27drm/i915: Enable/disable DRRSVandana Kannan
2015-01-27drm/i915: Make intel_crtc->config a pointerAnder Conselvan de Oliveira
2015-01-27drm/i915: Pass new_config down do crtc_compute_clockAnder Conselvan de Oliveira
2015-01-27drm/i915: Embedded struct drm_crtc_state in intel_crtc_stateAnder Conselvan de Oliveira
2015-01-27drm/i915: Rename struct intel_crtc_config to intel_crtc_stateAnder Conselvan de Oliveira
2014-12-15drm/i915: Consolidate DDI clock reading out in a single functionDamien Lespiau
2014-12-03drm/i915/skl: Update the DDI translation values for DP/eDP 1.3Damien Lespiau
2014-11-20drm/i915: Don't rely upon encoder->type for infoframe hw state readoutDaniel Vetter
2014-11-19drm/i915/ddi: set has_infoframe flag on DDI too v2Jesse Barnes
2014-11-18drm/i915/ddi: add break in DDI mode select switchJesse Barnes
2014-11-17drm/i915/skl: Use the pipe config DPLL tracking to query the link clockDamien Lespiau
2014-11-17drm/i915/skl: Set the eDP link rate on DPLL0Damien Lespiau
2014-11-17drm/i915: Introduce intel_psr.cRodrigo Vivi
2014-11-14drm/i915/skl: Fix big integer constant sparse warningDamien Lespiau
2014-11-14drm/i915/skl: Apply eDP WA only for gen < 9Vandana Kannan
2014-11-14drm/i915/skl: Implementation of SKL DPLL programmingSatheeshakrishna M
2014-11-14drm/i915/skl: Adjust the port PLL selection codeSatheeshakrishna M
2014-11-14drm/i915/skl: Define shared DPLLs for SkylakeSatheeshakrishna M
2014-11-14drm/i915/skl: Determine enabled PLL and its linkrate/pixel clockSatheeshakrishna M
2014-11-14drm/i915/skl: CD clock back calculation for SKLSatheeshakrishna M
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-06 17:16:05 +0000