Age | Commit message (Expand) | Author |
2023-10-10 | clk: tegra: fix error return case for recalc_rate | Timo Alho |
2023-07-27 | clk: tegra: tegra124-emc: Fix potential memory leak | Yuan Can |
2023-05-30 | clk: tegra20: fix gcc-7 constant overflow warning | Arnd Bergmann |
2022-10-26 | clk: tegra20: Fix refcount leak in tegra20_clock_init | Miaoqian Lin |
2022-10-26 | clk: tegra: Fix refcount leak in tegra114_clock_init | Miaoqian Lin |
2022-10-26 | clk: tegra: Fix refcount leak in tegra210_clock_init | Miaoqian Lin |
2022-04-15 | clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver | Miaoqian Lin |
2021-07-19 | clk: tegra: Ensure that PLLU configuration is applied properly | Dmitry Osipenko |
2021-01-27 | clk: tegra30: Add hda clock default rates to clock driver | Peter Geis |
2020-12-30 | clk: tegra: Do not return 0 on failure | Nicolin Chen |
2020-12-30 | clk: tegra: Fix duplicated SE clock entry | Dmitry Osipenko |
2020-10-07 | clk: tegra: Always program PLL_E when enabled | Thierry Reding |
2020-04-23 | clk: tegra: Fix Tegra PMC clock out parents | Sowjanya Komatineni |
2020-02-11 | clk: tegra: Mark fuse clock as critical | Stephen Warren |
2019-07-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
2019-06-28 | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds |
2019-06-25 | clk: tegra: Do not enable PLL_RE_VCO on Tegra210 | Thierry Reding |
2019-06-25 | clk: tegra: Warn if an enabled PLL is in IDDQ | Thierry Reding |
2019-06-25 | clk: tegra: Do not warn unnecessarily | Thierry Reding |
2019-06-25 | clk: tegra210: fix PLLU and PLLU_OUT1 | JC Kuo |
2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner |
2019-06-14 | clk: tegra210: Fix default rates for HDA clocks | Jon Hunter |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner |
2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner |
2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd |
2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd |
2019-05-07 | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-... | Stephen Boyd |
2019-04-25 | clk: tegra: divider: Mark Memory Controller clock as read-only | Dmitry Osipenko |
2019-04-25 | clk: tegra: emc: Replace BUG() with WARN_ONCE() | Dmitry Osipenko |
2019-04-25 | clk: tegra: emc: Fix EMC max-rate clamping | Dmitry Osipenko |
2019-04-25 | clk: tegra: emc: Support multiple RAM codes | Dmitry Osipenko |
2019-04-25 | clk: tegra: emc: Don't enable EMC clock manually | Dmitry Osipenko |
2019-04-25 | clk: tegra124: Remove lock-enable bit from PLLM | Dmitry Osipenko |
2019-04-25 | clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider | Dmitry Osipenko |
2019-04-23 | clk: core: replace clk_{readl,writel} with {readl,writel} | Jonas Gorski |
2019-04-19 | clk: tegra: Don't enable already enabled PLLs | Dmitry Osipenko |
2019-04-11 | clk: tegra: Make tegra_clk_super_mux_ops static | YueHaibing |
2019-03-14 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
2019-03-08 | Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ... | Stephen Boyd |
2019-02-22 | clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings | YueHaibing |
2019-02-18 | clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static | Wei Yongjun |
2019-02-15 | Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Arnd Bergmann |
2019-02-06 | clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 | Peter De Schrijver |
2019-02-06 | clk: tegra: dfll: add CVB tables for Tegra210 | Joseph Lo |
2019-02-06 | clk: tegra: dfll: round down voltages based on alignment | Joseph Lo |
2019-02-06 | clk: tegra: dfll: support PWM regulator control | Joseph Lo |
2019-02-06 | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo |
2019-02-06 | clk: tegra: dfll: registration for multiple SoCs | Peter De Schrijver |