| Age | Commit message (Expand) | Author |
|---|
| 2023-10-10 | clk: tegra: fix error return case for recalc_rate |   Timo Alho |
| 2023-05-30 | clk: tegra20: fix gcc-7 constant overflow warning |   Arnd Bergmann |
| 2022-10-26 | clk: tegra20: Fix refcount leak in tegra20_clock_init |   Miaoqian Lin |
| 2022-10-26 | clk: tegra: Fix refcount leak in tegra114_clock_init | Miaoqian Lin |
| 2022-10-26 | clk: tegra: Fix refcount leak in tegra210_clock_init | Miaoqian Lin |
| 2022-04-15 | clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver | Miaoqian Lin |
| 2021-07-20 | clk: tegra: Ensure that PLLU configuration is applied properly |   Dmitry Osipenko |
| 2021-01-27 | clk: tegra30: Add hda clock default rates to clock driver |   Peter Geis |
| 2020-12-30 | clk: tegra: Fix duplicated SE clock entry | Dmitry Osipenko |
| 2020-04-23 | clk: tegra: Fix Tegra PMC clock out parents |   Sowjanya Komatineni |
| 2020-02-11 | clk: tegra: Mark fuse clock as critical |   Stephen Warren |
| 2019-12-01 | clk: tegra20: Turn EMC clock gate into divider | Dmitry Osipenko |
| 2019-12-01 | clk: tegra: Fixes for MBIST work around |   Joseph Lo |
| 2019-09-16 | clk: tegra210: Fix default rates for HDA clocks |   Jon Hunter |
| 2019-09-16 | clk: tegra: Fix maximum audio sync clock for Tegra124/210 | Jon Hunter |
| 2019-08-06 | clk: tegra210: fix PLLU and PLLU_OUT1 |   JC Kuo |
| 2019-05-25 | clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider | Dmitry Osipenko |
| 2019-03-05 | clk: tegra: dfll: Fix a potential Oop in remove() |   Dan Carpenter |
| 2018-08-14 | Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',... |   Stephen Boyd |
| 2018-08-14 | Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te... | Stephen Boyd |
| 2018-07-25 | clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks |   Peter De-Schrijver |
| 2018-07-25 | clk: tegra: Add sdmmc mux divider clock | Peter De-Schrijver |
| 2018-07-25 | clk: tegra: Refactor fractional divider calculation | Peter De Schrijver |
| 2018-07-25 | clk: tegra: Fix includes required by fence_udelay() |   Aapo Vienamo |
| 2018-07-08 | clk: tegra: emc: Avoid out-of-bounds bug | Dmitry Osipenko |
| 2018-07-08 | clk: tegra: Mark Memory Controller clock as critical | Dmitry Osipenko |
| 2018-07-08 | clk: tegra: Make vde a child of pll_c3 |   Thierry Reding |
| 2018-07-08 | clk: tegra: Make vic03 a child of pll_c3 | Thierry Reding |
| 2018-07-08 | clk: tegra: bpmp: Don't crash when a clock fails to register |   Mikko Perttunen |
| 2018-06-12 | treewide: kzalloc() -> kcalloc() |   Kees Cook |
| 2018-06-04 | Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and... | Stephen Boyd |
| 2018-06-01 | clk: tegra: no need to check return value of debugfs_create functions |   Greg Kroah-Hartman |
| 2018-05-18 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 | Dmitry Osipenko |
| 2018-05-18 | clk: tegra20: Correct parents of CDEV1/2 clocks | Dmitry Osipenko |
| 2018-05-18 | clk: tegra20: Add DEV1/DEV2 OSC dividers | Dmitry Osipenko |
| 2018-03-12 | clk: tegra: Fix pll_u rate configuration |   Marcel Ziswiler |
| 2018-03-12 | clk: tegra: Specify VDE clock rate | Dmitry Osipenko |
| 2018-03-12 | clk: tegra20: Correct PLL_C_OUT1 setup | Dmitry Osipenko |
| 2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | Dmitry Osipenko |
| 2018-03-08 | clk: tegra: MBIST work around for Tegra210 | Peter De Schrijver |
| 2018-03-08 | clk: tegra: add fence_delay for clock registers | Peter De Schrijver |
| 2018-03-08 | clk: tegra: Add la clock for Tegra210 | Peter De Schrijver |
| 2017-11-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... |   Linus Torvalds |
| 2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman |
| 2017-11-01 | clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() |   Nicolin Chen |
| 2017-11-01 | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen |
| 2017-11-01 | clk: tegra: Fix cclk_lp divisor register |   Michał Mirosław |
| 2017-11-01 | clk: tegra: Bump SCLK clock rate to 216 MHz | Dmitry Osipenko |
| 2017-11-01 | clk: tegra: Use common definition of APBDMA clock gate | Dmitry Osipenko |
| 2017-11-01 | clk: tegra: Correct parent of the APBDMA clock | Dmitry Osipenko |
