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path: root/drivers/clk/tegra/clk-tegra30.c
AgeCommit message (Expand)Author
2019-09-16clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-11-18clk: tegra: Format tables consistentlyThierry Reding
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2015-05-13clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler
2015-04-10clk: tegra: Model oscillator as clockThierry Reding
2015-04-10clk: tegra: Use consistent indentationThierry Reding
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
2014-07-17ARM: tegra: Convert PMC to a driverThierry Reding
2014-07-17ARM: tegra: Move includes to include/soc/tegraThierry Reding
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren
2013-12-11clk: tegra: implement a reset driverStephen Warren
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver
2013-08-28clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan
2013-08-08clk: tegra30: Fix incorrect placement of __initdataSachin Kamat
2013-07-03Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds
2013-06-16ARM: tegra30: clocks: Fix pciex clock registrationJay Agarwal
2013-06-11clk: tegra: override bits for Tegra30 PLLMPeter De Schrijver
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad
2013-05-31clk: tegra: fix clk_out parents listPrashant Gaikwad
2013-05-04Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds
2013-04-09Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linu...Arnd Bergmann
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver
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