Age | Commit message (Expand) | Author |
---|---|---|
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
2019-05-16 | RISC-V: Avoid using invalid intermediate translations | Palmer Dabbelt |
2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
2019-04-25 | riscv: cleanup the parse_dtb calling conventions | Christoph Hellwig |
2019-04-25 | riscv: simplify the stack pointer setup in head.S | Christoph Hellwig |
2019-04-25 | riscv: clear all pending interrupts when booting | Christoph Hellwig |
2018-11-20 | RISC-V: Build flat and compressed kernel images | Anup Patel |
2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra |
2018-08-13 | RISC-V: Add the directive for alignment of stvec's value | Zong Li |
2018-02-20 | Rename sbi_save to parse_dtb to improve code readability | Michael Clark |
2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig |
2017-11-30 | RISC-V: move empty_zero_page definition to C and export it | Olof Johansson |
2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt |