diff options
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af')
14 files changed, 91 insertions, 18 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c index 5518e81a91e8..7366d25f86d0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -648,7 +648,7 @@ static void cgx_lmac_pause_frm_config(struct cgx *cgx, int lmac_id, bool enable) cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); cfg &= ~0xFFFFULL; cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, - cfg | (DEFAULT_PAUSE_TIME - 0x1000)); + cfg | (DEFAULT_PAUSE_TIME / 2)); cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME); @@ -657,7 +657,7 @@ static void cgx_lmac_pause_frm_config(struct cgx *cgx, int lmac_id, bool enable) CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); cfg &= ~0xFFFFULL; cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, - cfg | (DEFAULT_PAUSE_TIME - 0x1000)); + cfg | (DEFAULT_PAUSE_TIME / 2)); } else { /* ALL pause frames received are completely ignored */ cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); @@ -1161,6 +1161,18 @@ int cgx_get_phy_mod_type(void *cgxd, int lmac_id) return err; } +int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) +{ + struct cgx *cgx = cgxd; + u64 req = 0, resp; + + if (!cgx) + return -ENODEV; + + req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); + return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); +} + int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, int cgx_id, int lmac_id) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h index e9b6102bfef7..4445e23b688b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h @@ -83,7 +83,7 @@ #define CGX_COMMAND_REG CGXX_SCRATCH1_REG #define CGX_EVENT_REG CGXX_SCRATCH0_REG #define CGX_CMD_TIMEOUT 2200 /* msecs */ -#define DEFAULT_PAUSE_TIME 0xFFFF +#define DEFAULT_PAUSE_TIME 0x7FF #define CGX_NVEC 37 #define CGX_LMAC_FWI 0 @@ -162,4 +162,5 @@ void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable); int cgx_set_link_state(void *cgxd, int lmac_id, bool enable); int cgx_set_phy_mod_type(int mod, void *cgxd, int lmac_id); int cgx_get_phy_mod_type(void *cgxd, int lmac_id); +int cgx_get_phy_fec_stats(void *cgxd, int lmac_id); #endif /* CGX_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h index 1dc3059c9e0d..37a20d66246b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h @@ -129,6 +129,9 @@ enum cgx_cmd_id { CGX_CMD_GET_ADV_FEC, CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */ CGX_CMD_SET_PHY_MOD_TYPE, + CGX_CMD_PRBS, + CGX_CMD_DISPLAY_EYE, + CGX_CMD_GET_PHY_FEC_STATS, }; /* async event ids */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/net/ethernet/marvell/octeontx2/af/common.h index 4f8893ade710..9980598fe79e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -43,7 +43,7 @@ struct qmem { void *base; dma_addr_t iova; int alloc_sz; - u8 entry_sz; + u16 entry_sz; u8 align; u32 qsize; }; @@ -143,8 +143,13 @@ enum nix_scheduler { NIX_TXSCH_LVL_CNT = 0x5, }; -#define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1) -#define TXSCH_TL1_DFLT_RR_PRIO (0x1ull) +#define TXSCH_RR_QTM_MAX ((1 << 24) - 1) +#define TXSCH_TL1_DFLT_RR_QTM TXSCH_RR_QTM_MAX +#define TXSCH_TL1_DFLT_RR_PRIO (0x1ull) +#define MAX_SCHED_WEIGHT 0xFF +#define DFLT_RR_WEIGHT 71 +#define DFLT_RR_QTM ((DFLT_RR_WEIGHT * TXSCH_RR_QTM_MAX) \ + / MAX_SCHED_WEIGHT) /* Min/Max packet sizes, excluding FCS */ #define NIC_HW_MIN_FRS 40 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index 950ba1774ba7..8354572fa132 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -167,6 +167,7 @@ M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \ M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ cgx_set_link_mode_rsp) \ +M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ npa_lf_alloc_req, npa_lf_alloc_rsp) \ @@ -498,8 +499,17 @@ enum fec_type { }; struct phy_s { - u64 can_change_mod_type : 1; - u64 mod_type : 1; + struct { + u64 can_change_mod_type : 1; + u64 mod_type : 1; + u64 has_fec_stats : 1; + } misc; + struct fec_stats_s { + u32 rsfec_corr_cws; + u32 rsfec_uncorr_cws; + u32 brfec_corr_blks; + u32 brfec_uncorr_blks; + } fec_stats; }; struct cgx_lmac_fwdata_s { @@ -513,7 +523,7 @@ struct cgx_lmac_fwdata_s { /* Only applicable if SFP/QSFP slot is present */ struct sfp_eeprom_s sfp_eeprom; struct phy_s phy; -#define LMAC_FWDATA_RESERVED_MEM 1023 +#define LMAC_FWDATA_RESERVED_MEM 1021 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; }; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c index c85ee22b3d2b..8d1a0ec7ad9f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c @@ -131,7 +131,11 @@ int ptp_adjfine(struct ptp *ptp, long scaled_ppm) static inline u64 get_tsc(bool is_pmu) { +#if defined(CONFIG_ARM64) return is_pmu ? read_sysreg(pmccntr_el0) : read_sysreg(cntvct_el0); +#else + return 0; +#endif } int ptp_get_clock(struct ptp *ptp, bool is_pmu, u64 *clk, u64 *tsc) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 3868898757f6..1f877d2258d6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -707,6 +707,7 @@ static void rvu_setup_pfvf_macaddress(struct rvu *rvu) } else { eth_random_addr(pfvf->mac_addr); } + ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); /* Assign MAC address to VFs*/ rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); @@ -721,6 +722,7 @@ static void rvu_setup_pfvf_macaddress(struct rvu *rvu) } else { eth_random_addr(pfvf->mac_addr); } + ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); } } } @@ -1106,6 +1108,9 @@ static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) if (blkaddr < 0) return; + if (blkaddr == BLKADDR_NIX0) + rvu_nix_reset_mac(pfvf, pcifunc); + block = &hw->block[blkaddr]; num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index 5e90047b9a62..62e881254b8b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -266,7 +266,9 @@ struct rvu_pfvf { u16 minlen; bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ + bool pf_set_vfs_mac; u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ + u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ /* Broadcast pkt replication info */ u16 bcast_mce_idx; @@ -615,6 +617,7 @@ void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf); int rvu_nix_register_interrupts(struct rvu *rvu); void rvu_nix_unregister_interrupts(struct rvu *rvu); +void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); /* NPC APIs */ int rvu_npc_init(struct rvu *rvu); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c index e7f2a5678d57..145329cf5eaf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c @@ -906,6 +906,16 @@ int rvu_mbox_handler_cgx_get_phy_mod_type(struct rvu *rvu, struct msg_req *req, return 0; } +int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req, + struct msg_rsp *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_id, lmac_id; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id); +} + /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those * from its VFs as well. ie. NIX rx/tx counters at the CGX port level */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 52a590982ffd..55304fa55643 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -2910,10 +2910,11 @@ int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, if (nixlf < 0) return NIX_AF_ERR_AF_LF_INVALID; - /* Skip updating mac addr if request is from vf */ - if (!from_vf) - ether_addr_copy(pfvf->mac_addr, req->mac_addr); + /* VF can't overwrite admin(PF) changes */ + if (from_vf && pfvf->pf_set_vfs_mac) + return -EPERM; + ether_addr_copy(pfvf->mac_addr, req->mac_addr); rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, pfvf->rx_chan_base, req->mac_addr); @@ -3531,11 +3532,14 @@ void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) dev_err(rvu->dev, "CQ ctx disable failed\n"); } - /* Disabling CGX config done for PTP */ + /* Disabling CGX and NPC config done for PTP */ if (pfvf->hw_rx_tstamp_en) { rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); cgxd = rvu_cgx_pdata(cgx_id, rvu); cgx_lmac_ptp_config(cgxd, lmac_id, false); + /* Undo NPC config done for PTP */ + if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false)) + dev_err(rvu->dev, "NPC config for PTP failed\n"); pfvf->hw_rx_tstamp_en = false; } @@ -3968,3 +3972,12 @@ struct rvu *rvu, struct nix_inline_ipsec_lf_cfg *req, struct msg_rsp *rsp) return 0; } + +void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc) +{ + bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); + + /* overwrite vf mac address with default_mac */ + if (from_vf) + ether_addr_copy(pfvf->mac_addr, pfvf->default_mac); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c index 391f378c473f..b193d4bd3f81 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -2661,7 +2661,7 @@ int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, if (req->dir & PKIND_RX) { /* rx pkind set req valid only for cgx mapped PFs */ if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) - return -EPERM; + return 0; rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index c587b8dab336..212bfca5cf33 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -979,8 +979,10 @@ update_rule: pfvf->def_rule = rule; /* VF's MAC address is being changed via PF */ - if (pf_set_vfs_mac) - ether_addr_copy(pfvf->mac_addr, req->packet.dmac); + if (pf_set_vfs_mac) { + ether_addr_copy(pfvf->default_mac, req->packet.dmac); + pfvf->pf_set_vfs_mac = true; + } return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_sso.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_sso.c index 663fb2ce2865..dead90cb2f28 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_sso.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_sso.c @@ -27,8 +27,9 @@ #else #define rvu_sso_store_pair(val0, val1, addr) \ do { \ - *(uint64_t *)addr = val0; \ - *(uint64_t *)(((uint8_t *)addr) + 8) = val1; \ + u64 *addr1 = (void *)addr; \ + *addr1 = val0; \ + *(u64 *)(((u8 *)addr1) + 8) = val1; \ } while (0) #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_tim.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_tim.c index e79a6ddd33dd..e23c036eb023 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_tim.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_tim.c @@ -24,7 +24,9 @@ static inline u64 get_tenns_tsc(void) { u64 tsc; +#if defined(CONFIG_ARM64) asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); +#endif return tsc; } @@ -32,7 +34,9 @@ static inline u64 get_tenns_clk(void) { u64 tsc; +#if defined(CONFIG_ARM64) asm volatile("mrs %0, cntfrq_el0" : "=r" (tsc)); +#endif return tsc; } |