diff options
Diffstat (limited to 'Documentation')
4 files changed, 120 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8a88ddebc1a2..248acd840d11 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -99,6 +99,10 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * cache-lock: Enables cache locking for the allocated trace buffer. + As of now, this is supported only for secure buffer allocations + on Marvell OcteonTx2 platform. + * Optional property for CATU : * interrupts : Exactly one SPI may be listed for reporting the address error diff --git a/Documentation/devicetree/bindings/gpio/gpio-i2c.txt b/Documentation/devicetree/bindings/gpio/gpio-i2c.txt new file mode 100644 index 000000000000..ad2743bc65ed --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-i2c.txt @@ -0,0 +1,32 @@ +Device-Tree bindings for gpio i2c driver + +A simple parameterized no-irq of_driven i2c->gpio expander, +cut down from gpio-pcf857x.c to be totally device-tree driven. + +Suitable for any "memory-like" device, where a 1-byte i2c read yields data +which can safely be written back, possibly with a bit changed, with the +effect of changing only the output level of that bit's GPIO pin. + +Required properties: + - compatible = "gpio-i2c" + - reg = i2c-address + - gpio-controller + - #gpio-cells = <1>; + - ngpios = number of pins modeled + +Example nodes: + +&i2c_bus { + gpio1: cpld@6c { + compatible = "gpio-i2c"; + gpio-controller; + reg = <0x6c>; + #gpio-cells = <1>; + ngpios = <160>; // 8bits for each reg 0..0x13 + }; +}; + +_some_device_ { + // pin controlled by bitmask 0x2 of byte 0x4 of gpio1 + enable-gpios = <&gpio1 33>; +} diff --git a/Documentation/devicetree/bindings/mmc/cavium-mmc.txt b/Documentation/devicetree/bindings/mmc/cavium-mmc.txt index 1433e6201dff..21ed6d4fedcc 100644 --- a/Documentation/devicetree/bindings/mmc/cavium-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/cavium-mmc.txt @@ -17,16 +17,56 @@ Required properties: - clocks : phandle Optional properties: - - for cd, bus-width and additional generic mmc parameters - please refer to mmc.txt within this directory + - for cd, bus-width, vmmc-supply, vqmmc-supply, and additional generic + mmc parameters please refer to mmc.txt within this directory - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command - cavium,dat-clk-skew : number of coprocessor clocks before sampling data Deprecated properties: -- spi-max-frequency : use max-frequency instead -- cavium,bus-max-width : use bus-width instead -- power-gpios : use vmmc-supply instead -- cavium,octeon-6130-mmc-slot : use mmc-slot instead + - spi-max-frequency : use max-frequency instead + - cavium,bus-max-width : use bus-width instead + - power-gpios : use vmmc-supply instead + - cavium,octeon-6130-mmc-slot : use mmc-slot instead + +GPIO control via vmmc-supply & vqmmc-supply: + Two types of regulator object can be specified as mmc properties, + typically regulator-fixed controlled by GPIO pins. + + Octeon/OcteonTX chips commonly use GPIO8 as an MMC-reset pin. + In systems which may boot from MMC, it starts as input, and is gently + pulled up/down by board logic to indicate the active sense of the + signal. Chip reset then drives the signal in the opposite direction + to effect a reset of target devices. + Device tree should model this with a vmmc-supply regulator, gated by + GPIO8, so GPIO8 is driven in the non-reset direction when MMC devices + are probed, and held there until rmmod/shutdown/suspend. + This allows a warm reboot to reset the MMC devices. + + Octeon/OcteonTX MMC supports up to 3 mmc slots, but any + level-shifting to accommodate different signal voltages is + done by external hardware, under control of an optional + vqmmc regulator object, typically controlled by GPIO. + + If any mmc-slots have a vqmmc-supply property, it is taken as a warning + that we must switch carefully between slots (unless they have the same + vqmmc object), tri-stating MMC signals to avoid any transient states + as level-shifters are enabled/disabled. + + Even when so-called bi-directional level shifters are used, + this technique should be employed when using different bus-widths + on different slots, disabling level shifters to avoid presenting + non-uniform impedance across DATA0-7 & CMD when non-selected + 4-wide slots are left enabled, while accessing 8-wide targets. + + Note that it's not possible to specify multiple regulators + controlled by same GPIO pin, but with different active state. + If one GPIO line is require to switch voltage/routing between + different mmc-slots, specify a vqmmc-supply on one slot, but + not the other. The regulator_disable call on leaving that slot + will implicitly switch the state to support the unmarked slot. + + There's no need to list vqmmc-supply if all the mmc-slots on + a board run at same voltage, and have same width. Examples: mmc_1_4: mmc@1,4 { @@ -40,7 +80,8 @@ Examples: compatible = "mmc-slot"; reg = <0>; vmmc-supply = <&mmc_supply_3v3>; - max-frequency = <42000000>; + vqmmc-supply = <&vqmmc_3v3>; + max-frequency = <52000000>; bus-width = <4>; cap-sd-highspeed; }; @@ -49,7 +90,8 @@ Examples: compatible = "mmc-slot"; reg = <1>; vmmc-supply = <&mmc_supply_3v3>; - max-frequency = <42000000>; + vqmmc-supply = <&vqmmc_1v8>; + max-frequency = <100000000>; bus-width = <8>; cap-mmc-highspeed; non-removable; diff --git a/Documentation/devicetree/bindings/perf/arm_smmuv3_pmu.txt b/Documentation/devicetree/bindings/perf/arm_smmuv3_pmu.txt new file mode 100644 index 000000000000..39c95d5d03ef --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm_smmuv3_pmu.txt @@ -0,0 +1,34 @@ +* ARM SMMU-V3 PMU (Performance Monitor Extension) + +Required properties: + +- compatible: (standard compatible string) should be: + "arm,smmu-pmu-v3" + +- reg: (standard registers property) physical address and + size of the configuration registers blocks. + + SMMU-V3 PMU can have one or more Performance monitor + counter Group (PMCG). Each PMCG have one 4K page and + additional optional one more 4K page + +- msi-parent: See the generic MSI binding described in + devicetree/bindings/interrupt-controller/msi.txt + for a description of the msi-parent property. +Example: + + smmupmcg0@30100000 { + compatible = "arm,smmu-pmu-v3"; + + /* Single configuration register page */ + reg = <0x30100000 0x1000>; + msi-parent = <&its 0x10>; + }; + + smmupmcg0@830000100000 { + compatible = "arm,smmu-pmu-v3"; + + /* Additional optional configuration register page */ + reg = <0x30100000 0x1000>, <0x30110000 0x1000>; + msi-parent = <&its 0x11>; + }; |