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Diffstat (limited to 'Documentation/devicetree/bindings/net/xilinx_axienet.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/net/xilinx_axienet.txt | 135 |
1 files changed, 92 insertions, 43 deletions
diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt index 38f9ec076743..4cb9a50b7d2a 100644 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt @@ -1,55 +1,104 @@ -XILINX AXI ETHERNET Device Tree Bindings +XILINX AXI ETHERNET driver (xilinx_axienet) -------------------------------------------------------- -Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core -provides connectivity to an external ethernet PHY supporting different -interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two -segments of memory for buffering TX and RX, as well as the capability of -offloading TX/RX checksum calculation off the processor. +This driver supports following MAC configurations- +a) AXI 1G/2.5G Ethernet Subsystem. +b) 10G/25G High Speed Ethernet Subsystem. +c) 10 Gigabit Ethernet Subsystem. +d) USXGMII Ethernet Subsystem. -Management configuration is done through the AXI interface, while payload is -sent and received through means of an AXI DMA controller. This driver -includes the DMA driver code, so this driver is incompatible with AXI DMA -driver. +Management configuration is done through the AXI4-Lite interface. +The transmit and receive data interface is via the AXI4-Stream +interface connected to DMA controller. This driver supports Xilinx +AXI DMA and MCDMA DMA IP's. Programming sequence for these DMA IP's +is included in the xilinx_axienet driver. -For more details about mdio please refer phy.txt file in the same directory. +For details about MDIO please refer phy.txt [1]. Required properties: -- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", - "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" +- compatible : Must be one of "xlnx,axi-ethernet-1.00.a" or + "xlnx,axi-ethernet-1.01.a" or "xlnx,axi-ethernet-2.01.a" + for 1G MAC, + "xlnx,ten-gig-eth-mac" for 10 Gigabit Ethernet Subsystem, + "xlnx,xxv-ethernet-1.0" for 10G/25G MAC, + "xlnx,axi-2_5-gig-ethernet-1.0" for 2.5G MAC and + "xlnx,xxv-usxgmii-ethernet-1.0" for USXGMII. - reg : Address and length of the IO space. - interrupts : Should be a list of two interrupt, TX and RX. -- phy-handle : Should point to the external phy device. - See ethernet.txt file in the same directory. -- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware +- interrupt-parent : Must be core interrupt controller. +- phy-handle : See ethernet.txt [2]. +- local-mac-address : See ethernet.txt [2]. +- phy-mode : See ethernet.txt [2]. +- axistream-connected : Should contain phandle of DMA node. +Required properties (When AxiEthernet is configured with MCDMA): +- xlnx,channel-ids : Queue Identifier associated with the MCDMA Channel. +- interrupt-names : Should contain the interrupt names. Optional properties: -- phy-mode : See ethernet.txt -- xlnx,phy-type : Deprecated, do not use, but still accepted in preference - to phy-mode. -- xlnx,txcsum : 0 or empty for disabling TX checksum offload, - 1 to enable partial TX checksum offload, - 2 to enable full TX checksum offload -- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload - -Example: - axi_ethernet_eth: ethernet@40c00000 { - compatible = "xlnx,axi-ethernet-1.00.a"; - device_type = "network"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <2 0>; - phy-mode = "mii"; - reg = <0x40c00000 0x40000>; - xlnx,rxcsum = <0x2>; - xlnx,rxmem = <0x800>; - xlnx,txcsum = <0x2>; - phy-handle = <&phy0>; - axi_ethernetlite_0_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <1>; +- xlnx,rxmem : Max Rx Memory size. +- xlnx,txcsum : Tx checksum mode (Full, Partial and None). +- xlnx,rxcsum : Rx checksum mode (Full, Partial and None). +- xlnx,phy-type : Xilinx phy device type. See xilinx-phy.txt [3]. +- dma-coherent : Present if dma operations are coherent. +- xlnx,eth-hasnobuf : Used when 1G MAC is configured in non-processor mode. +- xlnx,rxtsfifo : Configures the axi fifo for receive timestamping. +- xlnx,eth-hasptp : Tells whether PTP is enabled in h/w or not. +- axififo-connected : Should contain the phandle of AXI stream fifo. +- clocks : Input clock specifier. Refer to common clock bindings. +- clock-names : Input clock names. Refer to IP PG for signal description. + 1G/2.5G: s_axi_lite_clk, axis_clk and ref_clk. + 10G/25G and USXGMII: s_axi_aclk, rx_core_clk and dclk. + 10 Gigabit: s_axi_aclk and dclk. + AXI DMA and MCDMA: m_axi_sg_aclk, m_axi_mm2s_aclk and + m_axi_s2mm_aclk. + +Optional properties (When AxiEthernet is configured with MCDMA): +- xlnx,num-queues : Number of queues/channels configured in h/w. +Optional properties (When USXGMII is in use): +- xlnx,usxgmii-rate : USXGMII PHY speed - can be 10, 100, 1000, 2500, + 5000 or 10000. +Optional properties for connected DMA node: +- xlnx,addrwidth : Specify the width of the DMA address space in bits. + Valid range is 32-64. Default is 32. +- xlnx,include-dre : Tells whether DMA h/w is configured with data + realignment engine(DRE) or not. + +NOTE: Time Sensitive Networking (TSN) related DT bindings are explained in [4]. + +[1] Documentation/devicetree/bindings/net/phy.txt +[2] Documentation/devicetree/bindings/net/ethernet.txt +[3] Documentation/devicetree/bindings/net/xilinx-phy.txt +[4] Documentation/devicetree/bindings/net/xilinx_tsn.txt + +Example: AXI 1G/2.5G Ethernet Subsystem + AXIDMA + + axi_eth_0_dma: dma@80040000 { + #dma-cells = <1>; + compatible = "xlnx,eth-dma"; + <snip> + }; + + axi_eth_0: ethernet@80000000 { + axistream-connected = <&axi_eth_0_dma>; + compatible = "xlnx,axi-ethernet-1.00.a"; + device_type = "network"; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 91 4>; + phy-handle = <&phy2>; + phy-mode = "sgmii"; + reg = <0x0 0x80000000 0x0 0x40000>; + xlnx,include-dre ; + xlnx,phy-type = <0x5>; + xlnx,rxcsum = <0x0>; + xlnx,rxmem = <0x1000>; + xlnx,txcsum = <0x0>; + axi_eth_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy2: phy@2 { + device_type = "ethernet-phy"; + reg = <2>; + }; }; - }; }; |