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2015-05-06drm/i915/chv: Remove DPIO force latency causing interpair skew issueweitee/gfx-patchClint Taylor
Latest version of the "CHV DPIO programming notes" no longer requires writes to TX DW 11 to fix a +2UI interpair skew issue. The current code from April 2014 was actually causing additional skew issues between all TMDS pairs. ver2: added same treatment to intel_dp.c based on Ville's testing. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit af8fcb9c58f1b2f02ddc04ba64710aaa52da00db) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Fix chv cdclk supportVille Syrjälä
The specs seem to be full of misinformation wrt. the Punit register 0x36. Some versions still show the old VLV bit layout, some the new layout, and all of them seem to tell us nonsense about the cdclk value encoding. Testing on actual hardware has shown that we simply need to program the desired CCK divider into the Punit register using the new layout of the bits. Doing that, the status bit change to indicate the same value, and the CCK 0x6b register also changes accordingly to indicate that CCK is now using the new divider. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 9d0d3fdaae08e9221070dda32348116c2a3235ed) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Increase the range of sideband address.Deepak S
Looks like latest BSW/CHV production system has sideband address > 128. Use u32 data types to cover new offset/address range :) Signed-off-by: Deepak S <deepak.s@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 707b6e3d3cfaf8e6a3a4f2c381e0b354848771c2) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Disable DDR DVFS on CHVVille Syrjälä
DDR DVFS introduces massive memory latencies which can't be handled by the PND deadline stuff. Instead the watermarks will need to be programmed to compensate for the latency and the deadlines will need to be programmed to tight fixed values. That means DDR DVFS can only be enabled if the display FIFOs are large enough, and that pretty much means we have to manually repartition them to suit the needs of the moment. That's a lot of change, so in the meantime let's just disable DDR DVFS to get the display(s) to be stable. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit fc1ac8dee1fe3d3155e8622e4d8e9130d88bc65b) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com> Conflicts: drivers/gpu/drm/i915/i915_reg.h
2015-05-06drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä
CHV has a new knob in Punit to select between some memory power savings modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is enabled, so let's do so in the hopes for moar power savings. v2: Put the thing into a separate function to avoid churn later v3: Don't break VLV Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit cfb41411fce52a8e8b6c1f0bd253d4ca7bfcbd0d) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Program PFI credits for VLVVidya Srinivas
PFI credit programming is required when CD clock (related to data flow from display pipeline to end display) is greater than CZ clock (related to data flow from memory to display plane). This programming should be done when all planes are OFF to avoid intermittent hangs while accessing memory even from different Gfx units (not just display). If cdclk/czclk >=1, PFI credits could be set as any number. To get better performance, larger PFI credit can be assigned to PND. Otherwise if cdclk/czclk<1, the default PFI credit of 8 should be set. v2: - Change log to lower log level instead of DRM_ERROR - Change function name to valleyview_program_pfi_credits - Move program PFI credits to modeset_init instead of intel_set_mode - Change magic numbers to logical constants [vsyrjala v3: - only program in response to cdclk update - program the credits also when cdclk<czclk - add CHV bits v4: - Change CHV cdclk<czclk credits to 12 (Vijay)] Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 1e69cd74af22cce3b882b155bef295ff68a40566) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä
Assuming the PND deadline mechanism works reasonably we should do memory requests as early as possible so that PND has schedule the requests more intelligently. Currently we're still calculating the watermarks as if VLV/CHV are identical to g4x, which isn't the case. The current code also seems to calculate insufficient watermarks and hence we're seeing some underruns, especially on high resolution displays. To fix it just rip out the current code and replace is with something that tries to utilize PND as efficiently as possible. We now calculate the WM watermark to trigger when the FIFO still has 256us worth of data. 256us is the maximum deadline value supoorted by PND, so issuing memory requests earlier would mean we probably couldn't utilize the full FIFO as PND would attempt to return the data at least in at least 256us. We also clamp the watermark to at least 8 cachelines as that's the magic watermark that enabling trickle feed would also impose. I'm assuming it matches some burst size. In theory we could just enable trickle feed and ignore the WM values, except trickle feed doesn't work with max fifo mode anyway, so we'd still need to calculate the SR watermarks. It seems cleaner to just disable trickle feed and calculate all watermarks the same way. Also trickle feed wouldn't account for the 256us max deadline value, thoguh that may be a moot point in non-max fifo mode sicne the FIFOs are fairly small. On VLV max fifo mode can be used with either primary or sprite planes. So the code now also checks all the planes (apart from the cursor) when calculating the SR plane watermark. We don't have to worry about the WM1 watermarks since we're using the PND deadline scheme which means the hardware ignores WM1 values. v2: Use plane->state->fb instead of plane->fb Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit ae80152ddad252f33893b92dd69f00cc53c5949f) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä
Poke at the CBR1_VLV register during init_clock_gating to make sure the PND deadline scheme is used. The hardware has two modes of operation wrt. watermarks: 1) PND deadline mode: - memory request deadline is calculated from actual FIFO level * DDL - WM1 watermark values are unused (AFAIK) - WM watermark level defines when to start fetching data from memory (assuming trickle feed is not used) 2) backup mode - deadline is based on FIFO status, DDL is unused - FIFO split into three regions with WM and WM1 watermarks, each part specifying a different FIFO status We want to use the PND deadline mode, so let's make sure the chicken bit is in the correct position on init. Also take the opportunity to refactor the shared code between VLV and CHV to a shared function. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit c6beb13ef33ae9430953deaa51db18a9e14277af) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä
VLV/CHV have similar DSPARB registers as older platforms, just more of them due to more planes. Add a bit of code to read out the current FIFO split from the registers. Will be useful later when we improve the WM calculations. v2: Add display_mmio_offset to DSPARB Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit b500472026e40ef2a4827a5973dc5424c98ede92) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Pass plane to vlv_compute_drain_latency()Ville Syrjälä
Now that we have drm_planes for the cursor and primary we can move the pixel_size handling into vlv_compute_drain_latency() and just pass the appropriate plane to it. v2: Check plane->state->fb instead of plane->fb Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Resolve conflict with Matt's s/plane->fb/plane->state->fb/ patch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 883a3d2f65212388b1577ebc020648fc95fa5d72) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com> Conflicts: drivers/gpu/drm/i915/intel_pm.c
2015-05-06drm/i915: Reorganize VLV DDL setupVille Syrjälä
Introduce struct vlv_wm_values to house VLV watermark/drain latency values. We start by using it when computing the drain latency values. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 0018fda1e4d5c076decc0dcf396ea4e3d3faa444) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com> Conflicts: drivers/gpu/drm/i915/intel_pm.c
2015-05-06drm/i915: Hide VLV DDL precision handlingVille Syrjälä
Move the DDL precision handling into vlv_compute_drain_latency() so the callers don't have to duplicate the same code to deal with it. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 341c526f43fdd2d85450bf5f72927a82dded4ee5) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com> Conflicts: drivers/gpu/drm/i915/intel_pm.c
2015-05-06drm/i915: Simplify VLV drain latency computationVille Syrjälä
The current drain lantency computation relies on hardcoded limits to determine when the to use the low vs. high precision multiplier. Rewrite the code to use a more straightforward approach. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit abfc00b545ba2c4dee1dcb124be59f34df3ed7d9) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä
Kill the silly DRAIN_LATENCY_PRECISION_* defines and just use the raw number instead. v2: Move the sprite 32/16 -> 16/8 preision multiplier change to another patch (Jesse) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 120305166aa8da2e8166d7ac1adce30194e6e24f) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä
Apparently we must yet halve the DDL drain latency from what we're using currently. This little nugget is not in any spec, but came down through the grapevine. This makes the displays a bit more stable. Not quite fully stable but at least they don't fall over immediately on driver load. v2: Update high_precision in valleyview_update_sprite_wm() too (Jesse) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit edf605601403194fdded0f8fd6305955d4ba009d) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Allow pixel clock up to 95% of cdclk on CHVVille Syrjälä
Supposedly CHV can sustain a pixel clock of up to 95% of cdclk, as opposed to the 90% limit that was used old older platforms. Update the cdclk selection code to allow for this. This will allow eg. HDMI 4k modes with their 297MHz pixel clock while still respecting the 320 MHz cdclk limit on CHV. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 6cca31950a5df57d89d9cb4f846c96dab902adf9) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
2015-05-06drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHzVille Syrjälä
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work. 4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 17fe10218be4663b0be1cf27805c32741eae48a8) Signed-off-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com> Conflicts: drivers/gpu/drm/i915/intel_display.c
2015-05-05Revert "intel_idle: Add support for the Airmont Core in the Cherrytrail and ↵Bruce Ashfield
Braswell SOCs" This reverts commit 4edc52a55f82ea26b59e801e6907c49bd1615fb1.
2015-05-05Revert "dmaengine: dw: Split device_control"Bruce Ashfield
This reverts commit 468bad4f7a6f428d010f53d7d9a2c5772ee3552d.
2015-05-05Revert "dmaengine: dw: provide DMA capabilities"Bruce Ashfield
This reverts commit 931304a6567e6d47914b43ff9af1be697c0dbd8a.
2015-05-05Revert "ACPI: Introduce has_acpi_companion()"Bruce Ashfield
This reverts commit 423e98721e048f6c7b925a75448f6c4ecb2b5b69.
2015-05-05Revert "x86/irq, ACPI: Implement ACPI driver to support IOAPIC hotplug"Bruce Ashfield
This reverts commit 934f85e8bfdbab9f3910d03f670799331f870444.
2015-04-28dmaengine: dw: don't handle interrupt when dmaengine is not usedJie Yang
When dma controller is not used by any user and set off, we should disble interrupt handler, at least the interrupt reset part, for some subsystem, e.g. ADSP, may use the dma in its own logic, here reset the interrupt may make this subsystem work abnormally. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> (cherry picked from commit 94b3eed7b8a4311f56a86b36430e9068b596ada4) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28dmaengine: dw: define DW_DMA_MAX_NR_MASTERSAndy Shevchenko
Instead of using magic number in the code the patch provides DW_DMA_MAX_NR_MASTERS constant. While here, restrict the reading of data width array by amount of the actual number of AHB masters. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> (cherry picked from commit d8ded50f8b26a224df48f9f93e49440c6a39b77f) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28dmaengine: dw: provide DMA capabilitiesAndy Shevchenko
The new DMAEngine requirement is to provide what the DMA controller can do, such as directions, bus widths, and residue granularity. The patch sets those properties for the DesignWare DMA controller driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> (cherry picked from commit 029a40e97d0db269f4a7fc02b0f29f627f628309) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28dmaengine: dw: Split device_controlMaxime Ripard
Split the device_control callback of the DesignWare DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> (cherry picked from commit a4b0d348f60122eb45c50b3e79a8edaec6fee534) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: i801: Use managed pcim_* PCI device initialization and reservationJarkko Nikula
Simplifies the code a bit and makes easier to disable PCI device on driver detach by removing the pcim_pin_device() call in the future if needed. Reason why i2c-i801.c doesn't ever call pci_disable_device() was because it made some systems to hang during power-off. See commit d6fcb3b9cf77 ("[PATCH] i2c-i801.c: don't pci_disable_device() after it was just enabled") and http://marc.info/?l=linux-kernel&m=115160053309535&w=2 Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit fef220da43d8537ed7d11da4db17b958cd779887) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: i801: Remove pci_enable_device() call from i801_resume()Jarkko Nikula
Since pci_disable_device() is not called from i801_suspend() and power state is set already it means that subsequent pci_enable_device() calls do practically nothing but monotonically increase struct pci_dev enable_cnt. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit f85da3f5de6f354bc26eb84c013b41a8b8558c5e) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: i801: Use managed devm_* memory and irq allocationJarkko Nikula
This simplifies the error and remove paths. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 1621c59d94d13380015fb5131acc6c14ecd1c797) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: i801: Remove i801_driver forward declarationJarkko Nikula
struct pci_driver i801_driver forward declaration is needed only for accessing the name field. Remove it and use dev_driver_string() instead. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 256493c58625530a958296724b92b344f3271b2f) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: i801: Don't break user-visible stringsJarkko Nikula
It makes more difficult to grep these error prints from sources if they are split to multiple source lines. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 9cbbf3dc994797f49cd30607a16182ca6c87863f) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28ACPI: Introduce has_acpi_companion()Rafael J. Wysocki
Now that the ACPI companions of devices are represented by pointers to struct fwnode_handle, it is not quite efficient to check whether or not an ACPI companion of a device is present by evaluating the ACPI_COMPANION() macro. For this reason, introduce a special static inline routine for that, has_acpi_companion(), and update the code to use it where applicable. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (cherry picked from commit ca5b74d2675a44f54aacb919c1cf022463e2f738) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: Suppress error message if platform_get_irq() < 0Alexey Brodkin
With -EPROBE_DEFER, this message is confusing and we hope for a centralized printout in the future anyhow. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Christian Ruppert <christian.ruppert@alitech.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit b20d386485e25934aef8aa24cbc8c2f51a2cb9cf) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware-pci: no need to provide clk_khzAndy Shevchenko
The clk_khz field makes sense only if SS counters are not provided. Since we provide them for Haswell and Baytrail explicitly we may omit the clk_khz parameter. Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit c99d49a964c700ad0bab5c54e2f559fce0487fad) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware-pci: remove Moorestown supportAndy Shevchenko
The Moorestown support bits were removed few years ago. This is a follow up to that changes. Suggested-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit bd1179fd5626f84d0ba177fdfb2e2bb1ced4c996) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: Add Intel Baytrail PMIC I2C bus supportDavid Box
This patch implements an I2C bus sharing mechanism between the host and platform hardware on select Intel BayTrail SoC platforms using the X-Powers AXP288 PMIC. On these platforms access to the PMIC must be shared with platform hardware. The hardware unit assumes full control of the I2C bus and the host must request access through a special semaphore. Hardware control of the bus also makes it necessary to disable runtime pm to avoid interfering with hardware transactions. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 894acb2f823b13afacfe40b02efbd9146af58586) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: fixup return handling of wait_for_completion_timeoutNicholas Mc Guire
return type of wait_for_completion_timeout is unsigned long not int, rather than introducing a new variable the wait_for_completion_timeout is moved into the if condition as the return value is only used to detect timeout. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 63d51e591931b878be7a16dacb37868a1e7ae8d1) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: Do not calculate SCL timing parameters needlesslyJarkko Nikula
Do SCL timing parameter calculation conditionally depending are custom parameters provided since calculated values will get instantly overwritten by provided parameters. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 42ffd3907c1663441cd1bd4d1a575930b63a5964) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: Add i2c bus locking supportDavid Box
Adds support for acquiring and releasing a hardware bus lock in the i2c designware core transfer function. This is needed for i2c bus controllers that are shared with but not controlled by the kernel. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit c0601d285efe063def984f91b04de2d227f89526) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28i2c: designware: use {readl|writel}_relaxed instead of readl/writelJisheng Zhang
readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache. This introduces i2c read/write delays on Marvell BG2/BG2Q SoCs when there are heavy L2 cache maintenance operations at the same time. The driver does not perform DMA, so it's safe to use the relaxed version. From another side, the relaxed io accessor macros are available on all architectures now, so we can use the relaxed versions instead. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> (cherry picked from commit 67105c5a94fbff6cc3a47e3ba65bacb3c706c5e6) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28serial: 8250_dw: Fix get_mctrl behaviourDesmond Liu
Fixed behaviour of get_mctrl() serial driver function as documented in: https://www.kernel.org/doc/Documentation/serial/driver Added device-tree properties 'dcd-override', 'dsr-override', 'cts-override', and 'ri-override' specific to the Synopsis 8250 DesignWare UART driver. Allows one to force Data Carrier Detect, Clear To Send, and Data Set Ready signals to permanently be reported as active. The Ring indicator can be forced to be reported as inactive. It is possible that if modem control signalling is enabled on a port that doesn't have these pins (e.g. - a simple two wire Tx/Rx port), the driver can hang indefinitely waiting for the state to change. The new DT properties allow the driver to ignore the state of these pins on serial ports that don't support them, as recommended in the kernel documentation. Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Signed-off-by: Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit dfd37668ea6d5029fb5d8a66ea5e202d0655fad7) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28serial: 8250: add support for ACPI-probed serial port for X-Gene platformFeng Kan
Enable APM X-Gene SoC serial port functionality when using ACPI table to initialize serial port. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 5e1aeea52f6a0763e79473b1767401fda88eb7e1) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28serial:8250:8250_pci: delete unneeded quirk entriesWang YanQing
These quirk entries have the same effect as default quirk entry, so we can just delete them. Signed-off-by: Wang YanQing <udknight@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 7cf91108d44dbef3d48766fd0e7f7347c2e48bda) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28serial:8250:8250_pci: fix redundant entry report for WCH_CH352_2SWang YanQing
Commit 8b5c913f7ee6464849570bacb6bcd9ef0eaf7dce ("serial: 8250_pci: Add WCH CH352 quirk to avoid Xscale detection") trigger one redundant entry report message. This patch fix it. Reported-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Wang YanQing <udknight@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 6262a3692b921a82075695c5c6d10f4a6bcc5fac) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28serial: 8250_pci: remove one useless explicit type conversionHeikki Krogerus
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 0a0d412abe473c37ddec8d3f6c0b84c58f1bb061) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28intel_idle: Add support for the Airmont Core in the Cherrytrail and Braswell ↵Len Brown
SOCs Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs. The states are similar to those of Silvermont in Baytrail, except both flavors of C6 states are faster. Signed-off-by: Len Brown <len.brown@intel.com> Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> (cherry picked from commit cab07a5652d1d124b505c2b7ed21c6823295c5d7) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28x86/irq, ACPI: Implement ACPI driver to support IOAPIC hotplugJiang Liu
Enable support of IOAPIC hotplug by: 1) reintroducing ACPI based IOAPIC driver 2) enhance pci_root driver to hook hotplug events The ACPI IOAPIC driver is always enabled if all of ACPI, PCI and IOAPIC are enabled. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Len Brown <lenb@kernel.org> Link: http://lkml.kernel.org/r/1414387308-27148-19-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (cherry picked from commit c183619b63ec934110e3a173a34b414e26869f96) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28ACPI / LPSS: check the result of ioremap()Heikki Krogerus
If it fails we have to skip the device. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (cherry picked from commit 4483d59e29fea65ef428be92a866aed50e28c795) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28pinctrl: update direction_output function of cherryview driverqipeng.zha
From the comments of gpiod_direction_output(), need to set @value as initial output, so update the lowlevel routine to make it work. Signed-off-by: jason.cj.chen<jason.cj.chen@intel.com> Signed-off-by: qipeng.zha <qipeng.zha@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 549e783f6a1504fcd24576302bc3818538b677f0) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
2015-04-28pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOsMika Westerberg
If the pin is in HiZ mode when it is requested as GPIO its value cannot be read (it always returns 0). In order to cope with the Linux GPIO subsystem where we do not have such state at all, turn the pin to be input instead. Reported-by: Jerome Blin <jerome.blin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 2479c7300ed943d62c88cd928ddccb4677c71ad4) Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-10 07:58:46 +0000