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authorManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-10-03 09:03:10 -0700
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2019-01-01 20:03:46 -0800
commitd261b05e1519bc719b3df7db14671b05c02dc0a3 (patch)
treeadcb4b7eb1e49a22ca363bf8294c6b3fa48424f4
parent0ecec9093b194ffcc3ea675b188252a8ac043941 (diff)
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tune-versal.inc: Add support for versal devices
Add tune file supporting versal devices. Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
-rw-r--r--meta-xilinx-bsp/conf/machine/include/tune-versal.inc14
1 files changed, 14 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/conf/machine/include/tune-versal.inc b/meta-xilinx-bsp/conf/machine/include/tune-versal.inc
new file mode 100644
index 0000000..83acf6e
--- /dev/null
+++ b/meta-xilinx-bsp/conf/machine/include/tune-versal.inc
@@ -0,0 +1,14 @@
+DEFAULTTUNE ?= "aarch64"
+SOC_FAMILY ?= "versal"
+
+# Available SOC_VARIANT's for versal:
+# virt
+
+SOC_VARIANT ?= ""
+
+require conf/machine/include/arm/arch-armv8.inc
+require conf/machine/include/soc-family.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "Image"
+