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From 6d2d7391ae48ce320e6a3a9efd21d2b40488ac19 Mon Sep 17 00:00:00 2001
From: David Andrey <david.andrey@netmodule.com>
Date: Fri, 27 Jun 2014 11:05:22 +0200
Subject: [PATCH 1/7] zx3: phy: micrel phy init
Use a custom init for Micrel KSZ9031
Each time the PL is loaded, the PHY goes in reset.
The PHY settings must be done again.
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Conflicts:
drivers/net/phy/micrel.c
include/linux/micrel_phy.h
---
drivers/net/phy/micrel.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5a8993b..412d144 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -27,6 +27,8 @@
#include <linux/micrel_phy.h>
#include <linux/of.h>
+#define NETMODULE_ZX3 /* some specific board init */
+
/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO 0x16
#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
@@ -148,9 +150,48 @@ static int ks8737_config_intr(struct phy_device *phydev)
return rc < 0 ? rc : 0;
}
+/*
+ * On the Enclustra ZX3 module, each FPGA reset leads
+ * to a PHY reset too. So let's do the setup again
+ * @@ netmodule, da
+ */
+static int zx3_config_init(struct phy_device *phydev)
+{
+ int err;
+
+ if (((phydev->phy_id & ~PHY_ID_KSZ9031) & phydev->drv->phy_id_mask) == 0) {
+
+ err = phy_write(phydev, 0xD, 0x0002);
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, 0xE, 0x0008); /* Reg 0x8 */
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, 0xD, 0x4002);
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, 0xE, 0x03FF); /* 3FF = max RXC and TXC delay */
+ if (err < 0)
+ return err;
+ }
+
+ else {
+ printk (KERN_ERR "ZX3 unsupported PHY ID\n");
+ }
+
+ return 0;
+}
+
static int kszphy_config_init(struct phy_device *phydev)
{
+#ifdef NETMODULE_ZX3
+ return zx3_config_init (phydev);
+#else
return 0;
+#endif
}
static int ksz8021_config_init(struct phy_device *phydev)
--
1.7.10.4
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