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|
&pruss_soc_bus0 {
uio_pruss1_mdio: uio_mdio@20ab2400 {
compatible = "ti,davinci_mdio";
reg = <0x20ab2400 0x90>;
clocks = <&k2g_clks 0x0014 1>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <2500000>;
status = "disabled";
};
uio_pruss1_mem: uio_pruss1_mem {
compatible = "ti,uio-module-drv";
mem = <0x20a80000 0x2000>,
<0x20a82000 0x2000>,
<0x20a90000 0x10000>,
<0x20aa0000 0x2000>,
<0x20aa6000 0x2000>,
<0x20aae000 0x31c>,
<0x20ab2000 0x70>;
mem-names = "dram0", "dram1", "shrdram2", "intc", "cfg",
"iep", "mii_rt";
status = "okay";
};
uio_pruss1_mem2: uio_pruss1_mem2 {
compatible = "ti,uio-module-drv";
mem = <0x20aa8000 0x38>,
<0x20ab0000 0x60>,
<0x20ab2400 0x90>,
<0x0c080000 0xe000>;
mem-names = "uart", "ecap", "mdio", "ocmc";
status = "okay";
};
uio_pruss1_evt0: uio_pruss1_evt0 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 224 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt1: uio_pruss1_evt1 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 225 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt2: uio_pruss1_evt2 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 226 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt3: uio_pruss1_evt3 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 227 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt4: uio_pruss1_evt4 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 228 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt6: uio_pruss1_evt6 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 230 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_evt7: uio_pruss1_evt7 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 231 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss1_0_mem: uio_pruss1_0_mem {
compatible = "ti,uio-module-drv";
mem = <0x20ab4000 0x3000>,
<0x20aa2000 0x400>,
<0x20aa2400 0x100>;
mem-names = "iram", "control", "debug";
status = "okay";
};
uio_pruss1_1_mem: uio_pruss1_1_mem {
compatible = "ti,uio-module-drv";
mem = <0x20ab8000 0x3000>,
<0x20aa4000 0x400>,
<0x20aa4400 0x100>;
mem-names = "iram", "control", "debug";
status = "okay";
};
};
&pruss_soc_bus1 {
uio_pruss2_mdio: uio_mdio@20af2400 {
compatible = "ti,davinci_mdio";
reg = <0x20af2400 0x90>;
clocks = <&k2g_clks 0x0015 1>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <2500000>;
status = "disabled";
};
uio_pruss2_mem: uio_pruss2_mem {
compatible = "ti,uio-module-drv";
mem = <0x20ac0000 0x2000>,
<0x20ac2000 0x2000>,
<0x20ad0000 0x10000>,
<0x20ae0000 0x2000>,
<0x20ae6000 0x2000>,
<0x20aee000 0x31c>,
<0x20af2000 0x70>;
mem-names = "dram0", "dram1", "shrdram2", "intc", "cfg",
"iep", "mii_rt";
status = "okay";
};
uio_pruss2_mem2: uio_pruss2_mem2 {
compatible = "ti,uio-module-drv";
mem = <0x20ae8000 0x38>,
<0x20af0000 0x60>,
<0x20af2400 0x90>,
<0x0c08e000 0xe000>;
mem-names = "uart", "ecap", "mdio", "ocmc";
status = "okay";
};
uio_pruss2_evt0: uio_pruss2_evt0 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 232 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt1: uio_pruss2_evt1 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 233 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt2: uio_pruss2_evt2 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 234 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt3: uio_pruss2_evt3 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 235 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt4: uio_pruss2_evt4 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 236 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt6: uio_pruss2_evt6 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 238 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_evt7: uio_pruss2_evt7 {
compatible = "ti,uio-module-drv";
interrupts = <GIC_SPI 239 0xf01>;
interrupt-mode = <0>;
status = "okay";
};
uio_pruss2_0_mem: uio_pruss2_0_mem {
compatible = "ti,uio-module-drv";
mem = <0x20af4000 0x3000>,
<0x20ae2000 0x400>,
<0x20ae2400 0x100>;
mem-names = "iram", "control", "debug";
status = "okay";
};
uio_pruss2_1_mem: uio_pruss2_1_mem {
compatible = "ti,uio-module-drv";
mem = <0x20af8000 0x3000>,
<0x20ae4000 0x400>,
<0x20ae4400 0x100>;
mem-names = "iram", "control", "debug";
status = "okay";
};
};
&k2g_pinctrl {
uio_pruss1_mdio_eth_default: uio_pruss1_mdio_eth_default {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x12cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* pr0_mdio_data.pr0_mdio_data */
K2G_CORE_IOPAD(0x12d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* pr0_mdio_mdclk.pr0_mdio_mdclk */
K2G_CORE_IOPAD(0x105c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3) /* gpmc_wait1.gpio0_23 (pr0_mii0_resetn) */
K2G_CORE_IOPAD(0x1070) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_csn2.gpio0_28 (pr0_mii0_intn) */
K2G_CORE_IOPAD(0x1054) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3) /* gpmc_be1n.gpio0_21 (pr0_mii1_resetn) */
K2G_CORE_IOPAD(0x1074) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_csn3.gpio0_29 (pr0_mii1_intn) */
/* PRUSS0 External Mux routing */
K2G_CORE_IOPAD(0x11d4) (BUFFER_CLASS_B | MUX_MODE3) /* uart0_ctsn.gpio0_106 */
K2G_CORE_IOPAD(0x11d8) (BUFFER_CLASS_B | MUX_MODE3) /* uart0_rtsn.gpio0_107 */
K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | MUX_MODE3) /* dcan0_rx.gpio1_57 */
K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | MUX_MODE3) /* dcan0_tx.gpio1_56 */
K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | MUX_MODE3) /* qspi_csn2.gpio1_66 */
K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | MUX_MODE3) /* qspi_csn3.gpio1_67 */
/* PRUSS0 PRU0 Ethernet */
K2G_CORE_IOPAD(0x122c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo0.pr0_pru0_gpi0 (pr0_mii0_rxd0) */
K2G_CORE_IOPAD(0x1230) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo1.pr0_pru0_gpi1 (pr0_mii0_rxd1) */
K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo2.pr0_pru0_gpi2 (pr0_mii0_rxd2) */
K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo3.pr0_pru0_gpi3 (pr0_mii0_rxd3) */
K2G_CORE_IOPAD(0x123c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo4.pr0_pru0_gpi4 (pr0_mii0_rxdv) */
K2G_CORE_IOPAD(0x1240) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo5.pr0_pru0_gpi5 (pr0_mii0_rxer) */
K2G_CORE_IOPAD(0x1244) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru0_gpo6.pr0_pru0_gpi6 (pr0_mii_mr0_clk) */
K2G_CORE_IOPAD(0x124c) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru0_gpo8.pr0_pru0_gpi8 (pr0_mii0_rxlink) */
K2G_CORE_IOPAD(0x1250) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo9.pr0_pru0_gpi9 (pr0_mii0_col) */
K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru0_gpo10.pr0_pru0_gpi10 (pr0_mii0_crs) */
K2G_CORE_IOPAD(0x12a8) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru1_gpo11.pr0_pru1_gpo11 (pr0_mii0_txd0) */
K2G_CORE_IOPAD(0x12ac) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru1_gpo12.pr0_pru1_gpo12 (pr0_mii0_txd1) */
K2G_CORE_IOPAD(0x12b0) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru1_gpo13.pr0_pru1_gpo13 (pr0_mii0_txd2) */
K2G_CORE_IOPAD(0x12b4) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru1_gpo14.pr0_pru1_gpo14 (pr0_mii0_txd3) */
K2G_CORE_IOPAD(0x12b8) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru1_gpo15.pr0_pru1_gpo15 (pr0_mii0_txen) */
K2G_CORE_IOPAD(0x12bc) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru1_gpo16.pr0_pru1_gpo16 (pr0_mii_mt0_clk) */
/* PRUSS0 PRU1 Ethernet */
K2G_CORE_IOPAD(0x127c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo0.pr0_pru1_gpi0 (pr0_mii1_rxd0) */
K2G_CORE_IOPAD(0x1280) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo1.pr0_pru1_gpi1 (pr0_mii1_rxd1) */
K2G_CORE_IOPAD(0x1284) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo2.pr0_pru1_gpi2 (pr0_mii1_rxd2) */
K2G_CORE_IOPAD(0x1288) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo3.pr0_pru1_gpi3 (pr0_mii1_rxd3) */
K2G_CORE_IOPAD(0x128c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo4.pr0_pru1_gpi4 (pr0_mii1_rxdv) */
K2G_CORE_IOPAD(0x1290) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo5.pr0_pru1_gpi5 (pr0_mii1_rxer) */
K2G_CORE_IOPAD(0x1294) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru1_gpo6.pr0_pru1_gpi6 (pr0_mii_mr1_clk) */
K2G_CORE_IOPAD(0x129c) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru1_gpo8.pr0_pru1_gpi8 (pr0_mii1_rxlink) */
K2G_CORE_IOPAD(0x12a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo9.pr0_pru1_gpi9 (pr0_mii1_col) */
K2G_CORE_IOPAD(0x12a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr0_pru1_gpo10.pr0_pru1_gpi10 (pr0_mii1_crs) */
K2G_CORE_IOPAD(0x1258) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru0_gpo11.pr0_pru0_gpo11 (pr0_mii1_txd0) */
K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru0_gpo12.pr0_pru0_gpo12 (pr0_mii1_txd1) */
K2G_CORE_IOPAD(0x1260) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru0_gpo13.pr0_pru0_gpo13 (pr0_mii1_txd2) */
K2G_CORE_IOPAD(0x1264) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru0_gpo14.pr0_pru0_gpo14 (pr0_mii1_txd3) */
K2G_CORE_IOPAD(0x1268) (BUFFER_CLASS_B | MUX_MODE0) /* pr0_pru0_gpo15.pr0_pru0_gpo15 (pr0_mii1_txen) */
K2G_CORE_IOPAD(0x126c) (BUFFER_CLASS_B | MUX_MODE1) /* pr0_pru0_gpo16.pr0_pru0_gpo16 (pr0_mii_mt1_clk) */
>;
};
uio_pruss2_mdio_eth_default: uio_pruss2_mdio_eth_default {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* pr1_mdio_data.pr1_mdio_data */
K2G_CORE_IOPAD(0x1378) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* pr1_mdio_mdclk.pr1_mdio_mdclk */
K2G_CORE_IOPAD(0x1050) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3) /* gpmc_be0ncle.gpio0_20 (pr1_mii0_resetn) */
K2G_CORE_IOPAD(0x1044) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_advnale.gpio0_17 (pr1_mii0_intn) */
K2G_CORE_IOPAD(0x1060) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3) /* gpmc_wpn.gpio0_24 (pr1_mii1_resetn) */
K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wait0.gpio0_22 (pr1_mii1_intn) */
/* PRUSS1 PRU0 Ethernet */
K2G_CORE_IOPAD(0x12d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo0.pr1_pru0_gpi0 (pr1_mii0_rxd0) */
K2G_CORE_IOPAD(0x12d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo1.pr1_pru0_gpi1 (pr1_mii0_rxd1) */
K2G_CORE_IOPAD(0x12dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo2.pr1_pru0_gpi2 (pr1_mii0_rxd2) */
K2G_CORE_IOPAD(0x12e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo3.pr1_pru0_gpi3 (pr1_mii0_rxd3) */
K2G_CORE_IOPAD(0x12e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo4.pr1_pru0_gpi4 (pr1_mii0_rxdv) */
K2G_CORE_IOPAD(0x12e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo5.pr1_pru0_gpi5 (pr1_mii0_rxer) */
K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru0_gpo6.pr1_pru0_gpi6 (pr1_mii_mr0_clk) */
K2G_CORE_IOPAD(0x12f4) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru0_gpo8.pr1_pru0_gpi8 (pr1_mii0_rxlink) */
K2G_CORE_IOPAD(0x12f8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo9.pr1_pru0_gpi9 (pr1_mii0_col) */
K2G_CORE_IOPAD(0x12fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru0_gpo10.pr1_pru0_gpi10 (pr1_mii0_crs) */
K2G_CORE_IOPAD(0x1350) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru1_gpo11.pr1_pru1_gpo11 (pr1_mii0_txd0) */
K2G_CORE_IOPAD(0x1354) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru1_gpo12.pr1_pru1_gpo12 (pr1_mii0_txd1) */
K2G_CORE_IOPAD(0x1358) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru1_gpo13.pr1_pru1_gpo13 (pr1_mii0_txd2) */
K2G_CORE_IOPAD(0x135c) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru1_gpo14.pr1_pru1_gpo14 (pr1_mii0_txd3) */
K2G_CORE_IOPAD(0x1360) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru1_gpo15.pr1_pru1_gpo15 (pr1_mii0_txen) */
K2G_CORE_IOPAD(0x1364) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru1_gpo16.pr1_pru1_gpo16 (pr1_mii_mt0_clk) */
/* PRUSS1 PRU1 Ethernet */
K2G_CORE_IOPAD(0x1324) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo0.pr1_pru1_gpi0 (pr1_mii1_rxd0) */
K2G_CORE_IOPAD(0x132c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo2.pr1_pru1_gpi2 (pr1_mii1_rxd2) */
K2G_CORE_IOPAD(0x1330) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo3.pr1_pru1_gpi3 (pr1_mii1_rxd3) */
K2G_CORE_IOPAD(0x1334) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo4.pr1_pru1_gpi4 (pr1_mii1_rxdv) */
K2G_CORE_IOPAD(0x1338) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo5.pr1_pru1_gpi5 (pr1_mii1_rxer) */
K2G_CORE_IOPAD(0x133c) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru1_gpo6.pr1_pru1_gpi6 (pr1_mii_mr1_clk) */
K2G_CORE_IOPAD(0x1344) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru1_gpo8.pr1_pru1_gpi8 (pr1_mii1_rxlink) */
K2G_CORE_IOPAD(0x1348) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo9.pr1_pru1_gpi9 (pr1_mii1_col) */
K2G_CORE_IOPAD(0x134c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* pr1_pru1_gpo10.pr1_pru1_gpi10 (pr1_mii1_crs) */
K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru0_gpo11.pr1_pru0_gpo11 (pr1_mii1_txd0) */
K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru0_gpo12.pr1_pru0_gpo12 (pr1_mii1_txd1) */
K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru0_gpo13.pr1_pru0_gpo13 (pr1_mii1_txd2) */
K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru0_gpo14.pr1_pru0_gpo14 (pr1_mii1_txd3) */
K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | MUX_MODE0) /* pr1_pru0_gpo15.pr1_pru0_gpo15 (pr1_mii1_txen) */
K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | MUX_MODE1) /* pr1_pru0_gpo16.pr1_pru0_gpo16 (pr1_mii_mt1_clk) */
>;
};
};
&uio_pruss1_mdio {
status = "okay";
pinctrl-0 = <&uio_pruss1_mdio_eth_default>;
pinctrl-names = "default";
reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
<&gpio0 21 GPIO_ACTIVE_LOW>;
reset-delay-us = <20>;
uio_pruss1_eth0_phy: uio-ethernet-phy@0 {
reg = <0>;
};
uio_pruss1_eth1_phy: uio-ethernet-phy@1 {
reg = <1>;
};
};
&uio_pruss2_mdio {
status = "okay";
pinctrl-0 = <&uio_pruss2_mdio_eth_default>;
pinctrl-names = "default";
reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
<&gpio0 24 GPIO_ACTIVE_LOW>;
reset-delay-us = <20>;
uio_pruss2_eth0_phy: uio-ethernet-phy@2 {
reg = <2>;
};
uio_pruss2_eth1_phy: uio-ethernet-phy@3 {
reg = <3>;
};
};
&pruss0 {
status = "disabled";
};
&pru0_0 {
status = "disabled";
};
&pru0_1 {
status = "disabled";
};
&pruss0_intc {
status = "disabled";
};
&pruss0_mdio {
status = "disabled";
};
&pruss1 {
status = "disabled";
};
&pru1_0 {
status = "disabled";
};
&pru1_1 {
status = "disabled";
};
&pruss1_intc {
status = "disabled";
};
&pruss1_mdio {
status = "disabled";
};
&pruss0_emac0 {
status = "disabled";
};
&pruss0_emac1 {
status = "disabled";
};
&pruss1_emac0 {
status = "disabled";
};
&pruss1_emac1 {
status = "disabled";
};
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