diff options
Diffstat (limited to 'recipes-kernel')
119 files changed, 10496 insertions, 200 deletions
diff --git a/recipes-kernel/images/esp-qcom-image.bb b/recipes-kernel/images/esp-qcom-image.bb new file mode 100644 index 0000000..2749752 --- /dev/null +++ b/recipes-kernel/images/esp-qcom-image.bb @@ -0,0 +1,20 @@ +DESCRIPTION = "EFI System Partition Image to boot Qualcomm boards" + +COMPATIBLE_HOST = '(x86_64.*|arm.*|aarch64.*)-(linux.*)' + +PACKAGE_INSTALL = " \ + kernel-devicetree \ + linux-qcom-uki \ + systemd-boot \ + systemd-bootconf \ +" + +KERNELDEPMODDEPEND = "" +KERNEL_DEPLOY_DEPEND = "" + +inherit image + +IMAGE_FSTYPES = "vfat" +IMAGE_FSTYPES_DEBUGFS = "" + +LINGUAS_INSTALL = "" diff --git a/recipes-kernel/images/initramfs-qcom-image.bb b/recipes-kernel/images/initramfs-qcom-image.bb new file mode 100644 index 0000000..411a096 --- /dev/null +++ b/recipes-kernel/images/initramfs-qcom-image.bb @@ -0,0 +1,5 @@ +require initramfs-rootfs-image.bb + +DESCRIPTION = "Ramdisk image for pivoting into rootfs extended to boot Qualcomm boards" + +PACKAGE_INSTALL += "packagegroup-qcom-boot" diff --git a/recipes-kernel/images/initramfs-rootfs-image.bb b/recipes-kernel/images/initramfs-rootfs-image.bb new file mode 100644 index 0000000..028f212 --- /dev/null +++ b/recipes-kernel/images/initramfs-rootfs-image.bb @@ -0,0 +1,27 @@ +DESCRIPTION = "Ramdisk image for pivoting into rootfs" + +PACKAGE_INSTALL = " \ + base-passwd \ + initramfs-module-copy-modules \ + initramfs-module-rootfs \ + initramfs-module-udev \ + ${VIRTUAL-RUNTIME_base-utils} \ + ${MACHINE_ESSENTIAL_EXTRA_RDEPENDS} \ + ${ROOTFS_BOOTSTRAP_INSTALL} \ +" + +# Do not pollute the initrd image with rootfs features +IMAGE_FEATURES = "debug-tweaks" +IMAGE_LINGUAS = "" + +LICENSE = "MIT" + +IMAGE_FSTYPES = "${INITRAMFS_FSTYPES}" +IMAGE_NAME_SUFFIX ?= "" +inherit core-image + +IMAGE_ROOTFS_SIZE = "8192" +IMAGE_ROOTFS_EXTRA_SPACE = "0" + +# Exclude all kernel images from the rootfs +PACKAGE_EXCLUDE = "kernel-image-*" diff --git a/recipes-kernel/images/linux-qcom-uki.bb b/recipes-kernel/images/linux-qcom-uki.bb new file mode 100644 index 0000000..0d34b60 --- /dev/null +++ b/recipes-kernel/images/linux-qcom-uki.bb @@ -0,0 +1,89 @@ +SUMMARY = "Qualcomm linux kernel UKI creation" + +DESCRIPTION = "Pack kernel image as a UKI (Unified Kernel Image) \ +by combining UEFI stub from systemd-boot, the kernel Image, initramfs, \ +optional dtb, osrelease info and other metadata like kernel cmdline." + +LICENSE = "BSD-3-Clause-Clear" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/BSD-3-Clause-Clear;md5=7a434440b651f4a472ca93716d01033a" + +COMPATIBLE_HOST = '(arm.*|aarch64.*)-(linux.*)' + +inherit python3native image-artifact-names linux-kernel-base + +DEPENDS = " systemd-boot-native python3-native python3-pefile-native \ + os-release systemd-boot virtual/kernel " + +require conf/image-uefi.conf + +KERNEL_VERSION = "${@get_kernelversion_file('${STAGING_KERNEL_BUILDDIR}')}" + +do_configure[depends] += " \ + systemd-boot:do_deploy \ + virtual/kernel:do_deploy \ + " +do_configure[depends] += "${@ '${INITRAMFS_IMAGE}:do_image_complete' if d.getVar('INITRAMFS_IMAGE') else ''}" + +do_compile() { + # Construct the ukify command + ukify_cmd="" + + # Ramdisk + if [ -n "${INITRAMFS_IMAGE}" ]; then + initrd="" + for img in ${INITRAMFS_FSTYPES}; do + if [ -e "${DEPLOY_DIR_IMAGE}/${INITRAMFS_IMAGE_NAME}.$img" ]; then + initrd="${DEPLOY_DIR_IMAGE}/${INITRAMFS_IMAGE_NAME}.$img" + break + fi + done + [ -f $initrd ] && echo "Creating UKI with $initrd" || bbfatal "$initrd is not a valid initrd to create UKI." + ukify_cmd="$ukify_cmd --initrd=$initrd" + fi + + # Kernel Image + # Note: systemd-boot can't handle compressed kernel image. + kernel_image="${DEPLOY_DIR_IMAGE}/Image" + [ -f $kernel_image ] && echo "Creating UKI with $kernel_image" || bbfatal "No valid kernel image to create UKI. Add 'Image' to KERNEL_IMAGETYPES." + ukify_cmd="$ukify_cmd --linux=$kernel_image" + + # Kernel version + ukify_cmd="$ukify_cmd --uname ${KERNEL_VERSION}" + + # Kernel cmdline + if [ -n "${KERNEL_CMDLINE_EXTRA}" ]; then + ukify_cmd="$ukify_cmd --cmdline='${KERNEL_CMDLINE_EXTRA}'" + fi + + # Architecture + ukify_cmd="$ukify_cmd --efi-arch ${EFI_ARCH}" + + # OS-release + osrelease="${RECIPE_SYSROOT}${libdir}/os-release" + ukify_cmd="$ukify_cmd --os-release @$osrelease" + + # Stub + stub="${DEPLOY_DIR_IMAGE}/linux${EFI_ARCH}.efi.stub" + [ -f $stub ] && echo "Creating UKI with $stub" || bbfatal "$stub is not a valid stub to create UKI." + ukify_cmd="$ukify_cmd --stub $stub" + + # Output + mkdir -p "${B}${EFI_UKI_PATH}" + output="${B}${EFI_UKI_PATH}/${EFI_LINUX_IMG}" + rm -f $output + ukify_cmd="$ukify_cmd --output=$output" + + # Call ukify to generate uki. + echo "ukify cmd:$ukify_cmd" + ukify build $ukify_cmd +} + +do_install() { + install -Dm 0755 ${B}${EFI_UKI_PATH}/${EFI_LINUX_IMG} ${D}${EFI_UKI_PATH}/${EFI_LINUX_IMG} +} + +FILES:${PN} = "${EFI_UKI_PATH}/${EFI_LINUX_IMG}" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +SKIP_RECIPE[linux-qcom-uki] ?= "${@bb.utils.contains('KERNEL_IMAGETYPES', 'Image', '', 'systemd-boot needs uncompressed kernel image. Add "Image" to KERNEL_IMAGETYPES.', d)}" diff --git a/recipes-kernel/linux-firmware/linux-firmware_%.bbappend b/recipes-kernel/linux-firmware/linux-firmware_%.bbappend index 5f10400..a60e935 100644 --- a/recipes-kernel/linux-firmware/linux-firmware_%.bbappend +++ b/recipes-kernel/linux-firmware/linux-firmware_%.bbappend @@ -1,7 +1,16 @@ -inherit update-alternatives +# To make the layer pass yocto-check-layer only inherit update-alternatives when building for qualcomm +ALTERNATIVES_CLASS = "" +ALTERNATIVES_CLASS:qcom = "update-alternatives" -ALTERNATIVE:${PN}-ath11k = "qca6390-board2" -ALTERNATIVE_LINK_NAME[qca6390-board2] = "/lib/firmware/ath11k/QCA6390/hw2.0/board-2.bin" +inherit ${ALTERNATIVES_CLASS} -ALTERNATIVE:${PN}-ath10k = "qca6174-board2" -ALTERNATIVE_LINK_NAME[qca6174-board2] = "/lib/firmware/ath10k/QCA6174/hw3.0/board-2.bin" +# firmware-ath6kl provides updated bdata.bin, which can not be accepted into main linux-firmware repo +ALTERNATIVE:${PN}-ath6k:qcom = "ar6004-hw13-bdata" +ALTERNATIVE_LINK_NAME[ar6004-hw13-bdata] = "${nonarch_base_libdir}/firmware/ath6k/AR6004/hw1.3/bdata.bin" + +ALTERNATIVE:${PN}-ath11k:qcom += "wcn6855-hw20-amss wcn6855-hw20-m3 wcn6855-hw20-regdb wcn6855-hw20-notice wcn6855-hw20-board-2" +ALTERNATIVE_LINK_NAME[wcn6855-hw20-amss] = "${nonarch_base_libdir}/firmware/ath11k/WCN6855/hw2.0/amss.bin" +ALTERNATIVE_LINK_NAME[wcn6855-hw20-m3] = "${nonarch_base_libdir}/firmware/ath11k/WCN6855/hw2.0/m3.bin" +ALTERNATIVE_LINK_NAME[wcn6855-hw20-regdb] = "${nonarch_base_libdir}/firmware/ath11k/WCN6855/hw2.0/regdb.bin" +ALTERNATIVE_LINK_NAME[wcn6855-hw20-notice] = "${nonarch_base_libdir}/firmware/ath11k/WCN6855/hw2.0/Notice.txt" +ALTERNATIVE_LINK_NAME[wcn6855-hw20-board-2] = "${nonarch_base_libdir}/firmware/ath11k/WCN6855/hw2.0/board-2.bin" diff --git a/recipes-kernel/linux/linux-linaro-qcom.inc b/recipes-kernel/linux/linux-linaro-qcom.inc index 40883f5..f7c1c96 100644 --- a/recipes-kernel/linux/linux-linaro-qcom.inc +++ b/recipes-kernel/linux/linux-linaro-qcom.inc @@ -3,7 +3,7 @@ # Released under the MIT license (see COPYING.MIT for the terms) DESCRIPTION ??= "Linaro Qualcomm Landing team ${PV} Kernel" -LICENSE = "GPLv2" +LICENSE = "GPL-2.0-only" LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46" inherit kernel @@ -15,7 +15,7 @@ SRCBRANCH = "release/qcomlt-${PV}" COMPATIBLE_MACHINE = "(qcom)" -LINUX_LINARO_QCOM_GIT ?= "git://git.linaro.org/landing-teams/working/qualcomm/kernel.git;protocol=https" +LINUX_LINARO_QCOM_GIT ?= "git://git.codelinaro.org/linaro/qcomlt/kernel.git;protocol=https" SRC_URI = "${LINUX_LINARO_QCOM_GIT};branch=${SRCBRANCH}" S = "${WORKDIR}/git" @@ -24,7 +24,7 @@ KERNEL_DEFCONFIG:aarch64 ?= "${S}/arch/arm64/configs/defconfig" KERNEL_DEFCONFIG:arm ?= "${S}/arch/arm/configs/qcom_defconfig" KERNEL_CONFIG_FRAGMENTS += "${S}/kernel/configs/distro.config" -require recipes-kernel/linux/linux-qcom-bootimg.inc +inherit linux-qcom-bootimg kernel_conf_variable() { sed -e "/CONFIG_$1[ =]/d;" -i ${B}/.config diff --git a/recipes-kernel/linux/linux-linaro-qcomlt-dev.bb b/recipes-kernel/linux/linux-linaro-qcomlt-dev.bb deleted file mode 100644 index 9aae535..0000000 --- a/recipes-kernel/linux/linux-linaro-qcomlt-dev.bb +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (C) 2014-2020 Linaro -# Released under the MIT license (see COPYING.MIT for the terms) -# -# This recipe is disabled by default. -# To enable it add the following line to conf/local.conf: -# PREFERRED_PROVIDER_virtual/kernel = "linux-linaro-qcomlt-dev" - -require recipes-kernel/linux/linux-linaro-qcom.inc - -DESCRIPTION = "Linaro Qualcomm Landing team Integration Kernel ${PV}" -SRCBRANCH = "integration-linux-qcomlt" - -# Set default SRCREV. it is statically set to the korg v3.7 tag, and -# hence prevent network access during parsing. If linux-linaro-qcomlt-dev -# is the preferred provider, they will be overridden to AUTOREV in following -# anonymous python routine and resolved when the variables are finalized. -SRCREV ?= '${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/kernel", "linux-linaro-qcomlt-dev", "${AUTOREV}", "29594404d7fe73cd80eaa4ee8c43dcc53970c60e", d)}' - -LINUX_VERSION = "5.11+" -PV = "${LINUX_VERSION}+git${SRCPV}" diff --git a/recipes-kernel/linux/linux-linaro-qcomlt_5.12.bb b/recipes-kernel/linux/linux-linaro-qcomlt_5.12.bb deleted file mode 100644 index 2587152..0000000 --- a/recipes-kernel/linux/linux-linaro-qcomlt_5.12.bb +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2014-2021 Linaro -# Released under the MIT license (see COPYING.MIT for the terms) - -require recipes-kernel/linux/linux-linaro-qcom.inc - -SRCBRANCH = "release/rb5/qcomlt-5.12" -SRCREV = "deeb40c41728645cd6971b1d7bd08281238caba0" - -COMPATIBLE_MACHINE = "(sm8250)" diff --git a/recipes-kernel/linux/linux-linaro-qcomlt_5.13.bb b/recipes-kernel/linux/linux-linaro-qcomlt_5.13.bb deleted file mode 100644 index 3636b5e..0000000 --- a/recipes-kernel/linux/linux-linaro-qcomlt_5.13.bb +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (C) 2014-2020 Linaro -# Released under the MIT license (see COPYING.MIT for the terms) - -require recipes-kernel/linux/linux-linaro-qcom.inc - -SRCREV = "1429722a220973e881d8cb5b5b486693457b4f11" diff --git a/recipes-kernel/linux/linux-linaro-qcomlt_5.14.bb b/recipes-kernel/linux/linux-linaro-qcomlt_5.14.bb deleted file mode 100644 index 0fc0f19..0000000 --- a/recipes-kernel/linux/linux-linaro-qcomlt_5.14.bb +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2014-2020 Linaro -# Released under the MIT license (see COPYING.MIT for the terms) - -require recipes-kernel/linux/linux-linaro-qcom.inc - -SRCBRANCH = "release/sa8155p-adp/qcomlt-5.14" -SRCREV = "4091a5657797a2e936231eb791ad6053cbaaff16" - -COMPATIBLE_MACHINE = "(sa8155p)" diff --git a/recipes-kernel/linux/linux-linaro-qcomlt_5.10.bb b/recipes-kernel/linux/linux-linaro-qcomlt_6.6.bb index f1652f0..dda348f 100644 --- a/recipes-kernel/linux/linux-linaro-qcomlt_5.10.bb +++ b/recipes-kernel/linux/linux-linaro-qcomlt_6.6.bb @@ -1,6 +1,6 @@ -# Copyright (C) 2014-2020 Linaro +# Copyright (C) 2021 Linaro # Released under the MIT license (see COPYING.MIT for the terms) require recipes-kernel/linux/linux-linaro-qcom.inc -SRCREV = "9ab492e76768cd1bd9f2da52004ed537c8b329f3" +SRCREV = "13f77d4021f2afbd93b08735e0aa076828d52357" diff --git a/recipes-kernel/linux/linux-qcom-bootimg.inc b/recipes-kernel/linux/linux-qcom-bootimg.inc deleted file mode 100644 index 9e3fef9..0000000 --- a/recipes-kernel/linux/linux-qcom-bootimg.inc +++ /dev/null @@ -1,146 +0,0 @@ -QIMG_DEPLOYDIR = "${WORKDIR}/qcom_deploy-${PN}" - -# Define INITRAMFS_IMAGE to create kernel+initramfs Android boot images in -# addition to default boot images. For example add the following line to your -# conf/local.conf: -# -# INITRAMFS_IMAGE = "initramfs-kerneltest-image" -# - -python __anonymous () { - if d.getVar('INITRAMFS_IMAGE') != '': - d.appendVarFlag('do_qcom_img_deploy', 'depends', ' ${INITRAMFS_IMAGE}:do_image_complete') -} - -python do_qcom_img_deploy() { - import shutil - import subprocess - - subdir = d.getVar("KERNEL_DEPLOYSUBDIR") - if subdir is not None: - qcom_deploy_dir = os.path.join(d.getVar("QIMG_DEPLOYDIR"), subdir) - image_dir = os.path.join(d.getVar("DEPLOY_DIR_IMAGE"), subdir) - else: - qcom_deploy_dir = d.getVar("QIMG_DEPLOYDIR") - image_dir = d.getVar("DEPLOY_DIR_IMAGE") - - initrd = None - if d.getVar('INITRAMFS_IMAGE') != '': - initrd_image_name = d.getVar("INITRAMFS_IMAGE_NAME") - baseinitrd = os.path.join(d.getVar("DEPLOY_DIR_IMAGE"), initrd_image_name) - for img in (".cpio.gz", ".cpio.lz4", ".cpio.lzo", ".cpio.lzma", ".cpio.xz", ".cpio"): - if os.path.exists(baseinitrd + img): - initrd = baseinitrd + img - break - if not initrd: - bb.fatal("Could not find initramfs image %s for bundling" % d.getVar("INITRAMFS_IMAGE")) - - B = d.getVar("B") - D = d.getVar("D") - kernel_output_dir = d.getVar("KERNEL_OUTPUT_DIR") - kernel_imagedest = d.getVar("KERNEL_IMAGEDEST") - kernel = os.path.join(B, "kernel-dtb") - definitrd = os.path.join(B, "initrd.img") - mkbootimg = os.path.join(d.getVar("STAGING_BINDIR_NATIVE"), "skales", "mkbootimg") - kernel_image_name = d.getVar("KERNEL_IMAGE_NAME") - kernel_link_name = d.getVar("KERNEL_IMAGE_LINK_NAME") - output_img = os.path.join(qcom_deploy_dir, "boot-%s.img" % (kernel_link_name)) - output_sd_img = os.path.join(qcom_deploy_dir, "boot-sd-%s.img" % (kernel_link_name)) - - arch = d.getVar("ARCH") - if arch is "arm": - kernel_name = "zImage" - elif arch is "arm64": - kernel_name = "Image.gz" - else: - bb.fatal("Unuspported ARCH %s" % arch) - - if os.path.exists(output_img): - os.unlink(output_img) - if os.path.exists(output_sd_img): - os.unlink(output_sd_img) - - with open(definitrd, "w") as f: - f.write("This is not an initrd\n") - - for dtbf in d.getVar("KERNEL_DEVICETREE").split(): - dtb = os.path.basename(dtbf) - dtb_name = dtb.rsplit('.', 1)[0] - - def getVarDTB(name): - return d.getVarFlag(name, dtb_name) or d.getVar(name) - - def make_image_internal(output, output_link, rootfs, initrd = definitrd): - subprocess.check_call([mkbootimg, - "--kernel", kernel, - "--ramdisk", initrd, - "--output", output, - "--pagesize", getVarDTB("QCOM_BOOTIMG_PAGE_SIZE"), - "--base", getVarDTB("QCOM_BOOTIMG_KERNEL_BASE"), - "--cmdline", "root=%s rw rootwait %s %s" % (rootfs, consoles, getVarDTB("KERNEL_CMDLINE_EXTRA") or "")]) - if os.path.exists(output_link): - os.unlink(output_link) - os.symlink(os.path.basename(output), output_link) - - def make_image(template, rootfs): - output = os.path.join(qcom_deploy_dir, template % (dtb_name, kernel_image_name)) - output_link = os.path.join(qcom_deploy_dir, template % (dtb_name, kernel_link_name)) - make_image_internal(output, output_link, rootfs) - return output - - def make_initramfs_image(template, rootfs, initrd, initrd_image_name): - output = os.path.join(qcom_deploy_dir, template % (initrd_image_name, dtb_name, kernel_image_name)) - output_link = os.path.join(qcom_deploy_dir, template % (initrd_image_name, dtb_name, kernel_link_name)) - make_image_internal(output, output_link, rootfs, initrd) - output_link = os.path.join(qcom_deploy_dir, template % ("initramfs", dtb_name, kernel_link_name)) - if os.path.exists(output_link): - os.unlink(output_link) - os.symlink(os.path.basename(output), output_link) - return output - - consoles = ' '.join(map(lambda c: "console=%(tty)s,%(rate)sn8" % dict(zip(("rate", "tty"), c.split(';'))), getVarDTB("SERIAL_CONSOLES").split())) - - # prepare kernel image with appended dtb - with open(kernel, 'wb') as wfd: - with open(os.path.join(kernel_output_dir, kernel_name), 'rb') as rfd: - shutil.copyfileobj(rfd, wfd) - with open(os.path.join(D, kernel_imagedest, dtb), 'rb') as rfd: - shutil.copyfileobj(rfd, wfd) - - rootfs = getVarDTB("QCOM_BOOTIMG_ROOTFS") - if not rootfs or rootfs is "": - bb.fatal("QCOM_BOOTIMG_ROOTFS is undefined") - - output = make_image("boot-%s-%s.img", rootfs) - if not os.path.exists(output_img): - os.symlink(os.path.basename(output), output_img) - - if initrd: - make_initramfs_image("boot-%s-%s-%s.img", rootfs, initrd, d.getVar("INITRAMFS_IMAGE")) - - sd_rootfs = getVarDTB("SD_QCOM_BOOTIMG_ROOTFS") - if sd_rootfs: - output = make_image("boot-sd-%s-%s.img", sd_rootfs) - if not os.path.exists(output_sd_img): - os.symlink(os.path.basename(output), output_sd_img) - - if initrd: - make_initramfs_image("boot-sd-%s-%s-%s.img", rootfs, initrd, d.getVar("INITRAMFS_IMAGE")) -} - -do_qcom_img_deploy[depends] += "skales-native:do_populate_sysroot" - -addtask qcom_img_deploy after do_populate_sysroot do_packagedata bundle_initramfs before do_deploy - -# Setup sstate, see deploy.bbclass -SSTATETASKS += "do_qcom_img_deploy" -do_qcom_img_deploy[sstate-inputdirs] = "${QIMG_DEPLOYDIR}" -do_qcom_img_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}" - -python do_qcom_img_deploy_setscene () { - sstate_setscene(d) -} -addtask do_qcom_img_deploy_setscene -do_qcom_img_deploy[dirs] = "${QIMG_DEPLOYDIR} ${B}" -do_qcom_img_deploy[cleandirs] = "${QIMG_DEPLOYDIR}" -do_qcom_img_deploy[stamp-extra-info] = "${MACHINE_ARCH}" diff --git a/recipes-kernel/linux/linux-yocto/0001-arm64-dts-qcom-qcm2290-temporarily-disable-cluster-i.patch b/recipes-kernel/linux/linux-yocto/0001-arm64-dts-qcom-qcm2290-temporarily-disable-cluster-i.patch new file mode 100644 index 0000000..80ff01e --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/0001-arm64-dts-qcom-qcm2290-temporarily-disable-cluster-i.patch @@ -0,0 +1,61 @@ +From bf26272a429b9e33ba5e8bc9ada9ec794b5e8610 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Wed, 19 Jul 2023 21:04:47 +0300 +Subject: [PATCH] arm64: dts: qcom: qcm2290: temporarily disable cluster idle + state + +For some reason cluster idle state causes the board to hang after boot. +Disable it to make it work properly. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate [need to find the issue first] +--- + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +index 1d1de156f8f0..d1f0aa828234 100644 +--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi ++++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +@@ -170,32 +170,34 @@ psci { + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; ++ //power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; ++ //power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; ++ //power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; +- power-domains = <&CLUSTER_PD>; ++ //power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + ++#if 0 + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; ++#endif + }; + + reserved_memory: reserved-memory { +-- +2.42.0 + diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.cfg new file mode 100644 index 0000000..c633a6a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: MIT + +CONFIG_ARCH_MSM8960=y +CONFIG_MSM_GCC_8960=y +CONFIG_MSM_LCC_8960=y +CONFIG_MSM_MMCC_8960=y +CONFIG_PINCTRL_APQ8064=y + +CONFIG_PHY_QCOM_APQ8064_SATA=y + +CONFIG_QCOM_CLK_RPM=y +CONFIG_REGULATOR_QCOM_RPM=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y + +# legacy boards +CONFIG_RPMSG_QCOM_SMD=y + +CONFIG_MSM_IOMMU=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.scc new file mode 100644 index 0000000..3040257 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-apq8064.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +#kconf hardware qcom-rpm.cfg +kconf hardware qcom-apq8064.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a-standard.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a-standard.scc new file mode 100644 index 0000000..240f154 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a-standard.scc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: MIT + +define KMACHINE qcom-armv7a +define KTYPE standard +define KARCH arm + +include ktypes/standard/standard.scc nocfg +branch qcom-armv7a + +include qcom-armv7a.scc + +#include features/bluetooth/bluetooth.scc +include features/cgroups/cgroups.scc +include features/fuse/fuse.scc +include features/transparent-hugepage/transparent-hugepage.cfg +include features/usb-net/usb-net.scc + +include cfg/fs/devtmpfs.scc +include cfg/fs/debugfs.scc +include cfg/fs/ext2.scc +include cfg/fs/ext4.scc +include cfg/fs/vfat.scc + +include cfg/timer/no_hz.scc + +#kconf hardware qcom-extra.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a.scc new file mode 100644 index 0000000..7006b1a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-armv7a.scc @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom.cfg + +include qcom-apq8064.scc +#include qcom-msm8974.scc + +include features/i2c/i2c.scc +include features/hrt/hrt.scc +include features/net/net.scc +include features/pci/pci.scc +include features/power/arm.scc +include features/spi/spi.scc +include features/usb/usb-base.scc +include features/leds/leds.scc +include features/pwm/pwm.scc + +include cfg/timer/rtc.scc +include cfg/dmaengine.scc diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.cfg new file mode 100644 index 0000000..3a21c88 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: MIT + +CONFIG_ARCH_MSM8974=y +CONFIG_MSM_GCC_8974=y +CONFIG_MSM_MMCC_8974=y +CONFIG_INTERCONNECT_QCOM_MSM8974=y +CONFIG_PINCTRL_MSM8X74=y + +CONFIG_EXTCON_QCOM_SPMI_MISC=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.scc new file mode 100644 index 0000000..eb866ed --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-msm8974.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpm.cfg +kconf hardware qcom-msm8974.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-rpm.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-rpm.cfg new file mode 120000 index 0000000..a39c26f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom-rpm.cfg @@ -0,0 +1 @@ +../qcom-armv8a/qcom-rpm.cfg
\ No newline at end of file diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom.cfg new file mode 100644 index 0000000..99eff38 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv7a/qcom.cfg @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: MIT + +CONFIG_ARCH_QCOM=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_CMA=y +CONFIG_DMA_CMA=y +CONFIG_ARM_THUMBEE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_VDSO=y + +CONFIG_SMP=y +CONFIG_SCHED_MC=y + +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y + +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_QCOM_SPM_CPUIDLE=y + +CONFIG_QCOM_SMSM=y + +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=m + +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_QCA=y + +CONFIG_COMMON_CLK_QCOM=y +CONFIG_KRAITCC=y +CONFIG_KPSS_XCC=y + +CONFIG_QCOM_GSBI=y + +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCOM_RNG=y + +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y + +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y + +CONFIG_MAILBOX=y + +CONFIG_MHI_BUS=m + +CONFIG_NVMEM=y +CONFIG_NVMEM_QCOM_QFPROM=y + +CONFIG_PCIE_QCOM=y + +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QCOM_SSBI_PMIC=y + +CONFIG_QCOM_Q6V5_ADSP=m +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_Q6V5_PAS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_Q6V5_WCSS=m +CONFIG_QCOM_WCNSS_PIL=m + +CONFIG_REMOTEPROC=y + +CONFIG_QCOM_APR=m +CONFIG_QCOM_FASTRPC=m +CONFIG_QCOM_IPA=m +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_ICC_BWMON=y + +CONFIG_SERIAL_DEV_BUS=y + +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m + +# CONFIG_MOUSE_PS2 is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_PMIC8XXX_PWRKEY=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y + +CONFIG_I2C_QUP=y +CONFIG_SPI_QUP=y + +CONFIG_MFD_PM8XXX=y +CONFIG_MFD_QCOM_RPM=y + +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MFD_SPMI_PMIC=y + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_REBOOT_MODE=y + +CONFIG_IIO=y +CONFIG_QCOM_SPMI_IADC=m + +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_ADC_TM5=m + +CONFIG_WATCHDOG_CORE=y +CONFIG_QCOM_WDT=y + +CONFIG_SLIMBUS=m + +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=y + +CONFIG_DRM=y +CONFIG_DRM_MSM=y +CONFIG_DRM_MSM_MDP4=y +CONFIG_DRM_MSM_MDP5=y +# CONFIG_DRM_MSM_DPU is not set +# CONFIG_DRM_MSM_DP is not set +CONFIG_DRM_MSM_DSI=y +CONFIG_DRM_MSM_DSI_28NM_PHY=y +CONFIG_DRM_MSM_DSI_20NM_PHY=y +CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y +# CONFIG_DRM_MSM_DSI_14NM_PHY is not set +# CONFIG_DRM_MSM_DSI_10NM_PHY is not set +# CONFIG_DRM_MSM_DSI_7NM_PHY is not set +CONFIG_DRM_MSM_HDMI=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y + +CONFIG_BACKLIGHT_CLASS_DEVICE=y + +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y + +CONFIG_EXTCON=y + +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_FS=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_MSM=y + +CONFIG_USB_DWC3=y + + +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y + +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_CRYPTO_MICHAEL_MIC=m + +CONFIG_LEDS_CLASS_MULTICOLOR=y +CONFIG_LEDS_QCOM_LPG=y + +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_DRV_PM8XXX=y + +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_OCMEM=y +CONFIG_QCOM_RMTFS_MEM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_SPM=y +CONFIG_QCOM_STATS=y +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_QCOM_SMP2P=y + +CONFIG_RESET_QCOM_PDC=y + +CONFIG_QCOM_PM8XXX_XOADC=y + +CONFIG_GENERIC_PHY=y +CONFIG_PHY_QCOM_QMP=y +# CONFIG_PHY_QCOM_QMP_PCIE is not set +# CONFIG_PHY_QCOM_QMP_UFS is not set +CONFIG_PHY_QCOM_QMP_USB=y +CONFIG_PHY_QCOM_USB_HS=y + +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_SLIM_QCOM_NGD_CTRL=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a-standard.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a-standard.scc new file mode 100644 index 0000000..499d0b2 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a-standard.scc @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: MIT + +define KMACHINE qcom-armv8a +define KTYPE standard +define KARCH arm64 + +include ktypes/standard/standard.scc nocfg +branch qcom-armv8a + +include qcom-armv8a.scc + +#include features/bluetooth/bluetooth.scc +include features/cgroups/cgroups.scc +include features/fuse/fuse.scc +include features/transparent-hugepage/transparent-hugepage.cfg +include features/usb-net/usb-net.scc + +include cfg/fs/devtmpfs.scc +include cfg/fs/debugfs.scc +include cfg/fs/ext2.scc +include cfg/fs/ext4.scc +include cfg/fs/vfat.scc + +include cfg/timer/no_hz.scc + +# enable the ability to run 32 bit apps +include arch/arm/32bit-compat.scc + +kconf hardware qcom-extra.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a.scc new file mode 100644 index 0000000..06ae07c --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-armv8a.scc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom.cfg + +include qcom-msm8916.scc +include qcom-msm8996.scc +include qcom-qcm2290.scc +include qcom-qcm6490.scc +include qcom-sdm845.scc +include qcom-sm6115.scc +include qcom-sm8250.scc +include qcom-sm8450.scc + +include features/i2c/i2c.scc +include features/hrt/hrt.scc +include features/net/net.scc +include features/pci/pci.scc +include features/power/arm.scc +include features/spi/spi.scc +include features/usb/usb-base.scc +include features/leds/leds.scc +include features/pwm/pwm.scc + +include cfg/timer/rtc.scc +include cfg/dmaengine.scc diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-extra.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-extra.cfg new file mode 100644 index 0000000..10a8e86 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-extra.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: MIT + +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUP_BPF=y + +CONFIG_AUTOFS_FS=y + +CONFIG_TYPEC_MUX_GPIO_SBU=y +CONFIG_TYPEC_MUX_NB7VPQ904M=y +CONFIG_TYPEC_MUX_FSA4480=y +CONFIG_TYPEC_DP_ALTMODE=y + +CONFIG_DRM_LONTIUM_LT9611=y +CONFIG_DRM_LONTIUM_LT9611UXC=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y + +CONFIG_USB_XHCI_PCI_RENESAS=y + +CONFIG_USB_HSIC_USB3503=y + +CONFIG_PERF_EVENTS=y + +CONFIG_USB_HUB_USB251XB=y + +CONFIG_ATL1C=m + +CONFIG_CAN=m +CONFIG_CAN_MCP251XFD=m + +CONFIG_BACKLIGHT_PWM=m +CONFIG_DRM_PANEL_NOVATEK_NT36672E=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.cfg new file mode 100644 index 0000000..9c9a712 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_MSM8916=y + +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_CLK_APCS_MSM8916=y +CONFIG_MSM_GCC_8916=y + +CONFIG_INTERCONNECT_QCOM_MSM8916=y + +CONFIG_QCOM_IOMMU=y + +CONFIG_PM8916_WATCHDOG=y + +CONFIG_SND_SOC_APQ8016_SBC=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m + +CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y + +CONFIG_USB_ULPI_BUS=y +CONFIG_PHY_QCOM_USB_HS=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_VADC=y + +CONFIG_QCOM_SMSM=y + +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_MSM=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y + +CONFIG_WCN36XX=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.scc new file mode 100644 index 0000000..4b21237 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8916.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpm.cfg +kconf hardware qcom-msm8916.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.cfg new file mode 100644 index 0000000..d636c96 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_MSM8996=y + +CONFIG_QCOM_CLK_APCC_MSM8996=y +CONFIG_MSM_GCC_8996=y +CONFIG_MSM_MMCC_8996=y +CONFIG_INTERCONNECT_QCOM_MSM8996=y + +CONFIG_PHY_QCOM_QMP_PCIE_8996=y + +CONFIG_SND_SOC_MSM8996=m + +CONFIG_SND_SOC_WCD9335=m + +CONFIG_PHY_QCOM_QUSB2=y + +CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_VADC=y + +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.scc new file mode 100644 index 0000000..ef71826 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-msm8996.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpm.cfg +kconf hardware qcom-msm8996.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.cfg new file mode 100644 index 0000000..1ff457d --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_QCM2290=y +CONFIG_QCM_GCC_2290=y +CONFIG_QCM_DISPCC_2290=y +CONFIG_INTERCONNECT_QCOM_QCM2290=y + +CONFIG_PHY_QCOM_QUSB2=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.scc new file mode 100644 index 0000000..ab2f061 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm2290.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpm.cfg +kconf hardware qcom-qcm2290.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.cfg new file mode 100644 index 0000000..a1da8cb --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_SC7280=y +CONFIG_PINCTRL_SC7280_LPASS_LPI=m +CONFIG_SND_SOC_SC7280=m +CONFIG_INTERCONNECT_QCOM_SC7280=y + +CONFIG_SC_CAMCC_7280=m +CONFIG_SC_DISPCC_7280=y +CONFIG_SC_GCC_7280=y +CONFIG_SC_GPUCC_7280=y +CONFIG_SC_LPASS_CORECC_7280=m +CONFIG_SC_VIDEOCC_7280=m + +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_USB_DWC3_QCOM=y +CONFIG_PHY_QCOM_QMP_COMBO=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.scc new file mode 100644 index 0000000..bf53a47 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-qcm6490.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpmh.cfg +kconf hardware qcom-qcm6490.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpm.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpm.cfg new file mode 100644 index 0000000..7fb1025 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpm.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: MIT + +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_QCOM_MPM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_CLK_SMD_RPM=y + +# legacy boards +CONFIG_RPMSG_QCOM_SMD=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpmh.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpmh.cfg new file mode 100644 index 0000000..f914280 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-rpmh.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: MIT + +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_AOSS_QMP=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_QCOM_CLK_RPMH=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.cfg new file mode 100644 index 0000000..ee337aa --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_SDM845=y +CONFIG_SDM_CAMCC_845=m +CONFIG_SDM_GCC_845=y +CONFIG_SDM_GPUCC_845=y +CONFIG_SDM_VIDEOCC_845=m +CONFIG_SDM_DISPCC_845=y +CONFIG_INTERCONNECT_QCOM_SDM845=y + +CONFIG_MFD_WCD934X=m +CONFIG_GPIO_WCD934X=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_SDM845=m + +CONFIG_QCOM_LMH=y +CONFIG_PHY_QCOM_QUSB2=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_ADC5=y + +CONFIG_QCOM_SPMI_RRADC=m +CONFIG_REGULATOR_QCOM_LABIBB=m + +CONFIG_ATH10K=m +CONFIG_ATH10K_SNOC=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.scc new file mode 100644 index 0000000..0446f2a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sdm845.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpmh.cfg +kconf hardware qcom-sdm845.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.cfg new file mode 100644 index 0000000..2bb223a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_SM6115=y +CONFIG_SM_DISPCC_6115=y +CONFIG_SM_GCC_6115=y +CONFIG_SM_GPUCC_6115=y +CONFIG_INTERCONNECT_QCOM_SM6115=y + +CONFIG_PHY_QCOM_QUSB2=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_ADC5=y diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.scc new file mode 100644 index 0000000..a7411aa --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm6115.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpm.cfg +kconf hardware qcom-sm6115.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.cfg new file mode 100644 index 0000000..25fc04f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_SM8250=y +CONFIG_PINCTRL_SM8250_LPASS_LPI=m +CONFIG_SM_CAMCC_8250=m +CONFIG_SM_DISPCC_8250=y +CONFIG_SM_GCC_8250=y +CONFIG_SM_GPUCC_8250=y +CONFIG_SM_VIDEOCC_8250=m +CONFIG_CLK_GFM_LPASS_SM8250=m +CONFIG_INTERCONNECT_QCOM_SM8250=y + +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_SM8250=m + +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_QCOM_PMIC=y + +CONFIG_QCOM_IPCC=y + +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_ADC5=y + +CONFIG_MFD_QCOM_QCA639X=y + +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.scc new file mode 100644 index 0000000..cbd485d --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8250.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpmh.cfg +kconf hardware qcom-sm8250.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.cfg new file mode 100644 index 0000000..88939b0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: MIT + +CONFIG_PINCTRL_SM8450=y +CONFIG_PINCTRL_SM8450_LPASS_LPI=m +CONFIG_SM_CAMCC_8450=m +CONFIG_SM_DISPCC_8450=y +CONFIG_SM_GCC_8450=y +CONFIG_SM_GPUCC_8450=y +CONFIG_SM_VIDEOCC_8450=m +CONFIG_INTERCONNECT_QCOM_SM8450=y + +CONFIG_QCOM_IPCC=y + +CONFIG_TYPEC_UCSI=y +CONFIG_UCSI_PMIC_GLINK=y +CONFIG_QCOM_PMIC_GLINK=y +CONFIG_BATTERY_QCOM_BATTMGR=m + +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y + +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_SPMI_ADC5=y + +CONFIG_MFD_QCOM_QCA639X=y + +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.scc b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.scc new file mode 100644 index 0000000..d9a02c0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom-sm8450.scc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT + +kconf hardware qcom-rpmh.cfg +kconf hardware qcom-sm8450.cfg diff --git a/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom.cfg b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom.cfg new file mode 100644 index 0000000..e969e08 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/bsp/qcom-armv8a/qcom.cfg @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: MIT + +CONFIG_ARCH_QCOM=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM_QCOM_CPUFREQ_HW=y +CONFIG_CMA=y +CONFIG_DMA_CMA=y + +CONFIG_SCHED_MC=y + +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=m + +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_QCA=y + +CONFIG_COMMON_CLK_QCOM=y + +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCOM_RNG=y + +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y + +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_OSM_L3=y + +CONFIG_MAILBOX=y +CONFIG_QCOM_APCS_IPC=y + +CONFIG_MHI_BUS=m + +CONFIG_NVMEM=y +CONFIG_NVMEM_QCOM_QFPROM=y + +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_QCOM=y + +CONFIG_PCIE_QCOM=y +CONFIG_PCIE_QCOM_EP=m + +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y + +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_LPASS_LPI=m +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y + +CONFIG_QCOM_Q6V5_ADSP=m +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_Q6V5_PAS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_Q6V5_WCSS=m +CONFIG_QCOM_WCNSS_PIL=m + +CONFIG_REMOTEPROC=y + +CONFIG_QCOM_APR=m +CONFIG_QCOM_FASTRPC=m +CONFIG_QCOM_IPA=m +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_ICC_BWMON=y + +CONFIG_SERIAL_DEV_BUS=y + +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m + +# CONFIG_MOUSE_PS2 is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y + +CONFIG_QCOM_GENI_SE=y +CONFIG_SERIAL_QCOM_GENI=y +CONFIG_SERIAL_QCOM_GENI_CONSOLE=y +CONFIG_I2C_QCOM_GENI=y +CONFIG_I2C_QUP=y +CONFIG_SPI_QUP=y +CONFIG_SPI_QCOM_GENI=y + +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MFD_SPMI_PMIC=y + +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_REBOOT_MODE=y + +CONFIG_IIO=y +CONFIG_QCOM_SPMI_IADC=m + +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_ADC_TM5=m + +CONFIG_WATCHDOG_CORE=y +CONFIG_QCOM_WDT=y + +CONFIG_SLIMBUS=m + +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=y + +CONFIG_DRM=y +CONFIG_DRM_MSM=y +CONFIG_DRM_MSM_MDP5=y +CONFIG_DRM_MSM_DPU=y +CONFIG_DRM_MSM_DP=y +CONFIG_DRM_MSM_DSI=y +CONFIG_DRM_MSM_DSI_28NM_PHY=y +CONFIG_DRM_MSM_DSI_20NM_PHY=y +CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y +CONFIG_DRM_MSM_DSI_14NM_PHY=y +CONFIG_DRM_MSM_DSI_10NM_PHY=y +CONFIG_DRM_MSM_DSI_7NM_PHY=y +CONFIG_DRM_MSM_HDMI=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y + +CONFIG_BACKLIGHT_CLASS_DEVICE=y + +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y + +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m + +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m + +CONFIG_TYPEC=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_FS=y + +CONFIG_USB_XHCI_HCD=y + +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y + +CONFIG_SCSI=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y + +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_CRYPTO_MICHAEL_MIC=m + +CONFIG_LEDS_CLASS_MULTICOLOR=y +CONFIG_LEDS_QCOM_LPG=y + +CONFIG_USB_DWC3=y + +CONFIG_RAS=y +CONFIG_EDAC=y +CONFIG_EDAC_QCOM=y + +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_DRV_PM8XXX=y + +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GPI_DMA=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_OCMEM=y +CONFIG_QCOM_RMTFS_MEM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_STATS=y +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_QCOM_SMP2P=y + +CONFIG_RESET_QCOM_AOSS=y +CONFIG_RESET_QCOM_PDC=y +CONFIG_QCOM_PDC=y + +CONFIG_I2C_QCOM_CCI=m + +CONFIG_GENERIC_PHY=y +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QMP_PCIE=y +CONFIG_PHY_QCOM_QMP_UFS=y +CONFIG_PHY_QCOM_QMP_USB=y + +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_SLIM_QCOM_NGD_CTRL=m + +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_QCOM_CAMSS=m +CONFIG_VIDEO_QCOM_VENUS=m + +CONFIG_CORESIGHT=m +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m +CONFIG_CORESIGHT_SINK_TPIU=m +CONFIG_CORESIGHT_SOURCE_ETM4X=m +CONFIG_CORESIGHT_STM=m +CONFIG_CORESIGHT_CPU_DEBUG=m +CONFIG_CORESIGHT_CTI=m +CONFIG_CORESIGHT_TPDM=m +CONFIG_CORESIGHT_TPDA=m diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/0001-FROMLIST-dma-heap-Add-proper-kref-handling-on-dma-bu.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/0001-FROMLIST-dma-heap-Add-proper-kref-handling-on-dma-bu.patch new file mode 100644 index 0000000..87fefa9 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/0001-FROMLIST-dma-heap-Add-proper-kref-handling-on-dma-bu.patch @@ -0,0 +1,145 @@ +From dd2c03120004f3bfed8b4f6500c33957b1bae807 Mon Sep 17 00:00:00 2001 +From: John Stultz <jstultz@google.com> +Date: Mon, 11 Sep 2023 10:30:31 +0800 +Subject: [PATCH 1/2] FROMLIST: dma-heap: Add proper kref handling on dma-buf + heaps + +Add proper refcounting on the dma_heap structure. +While existing heaps are built-in, we may eventually +have heaps loaded from modules, and we'll need to be +able to properly handle the references to the heaps + +Also moves minor tracking into the heap structure so +we can properly free things. + +[Yong: Just add comment for "minor" and "refcount"] +Signed-off-by: John Stultz <jstultz@google.com> +Signed-off-by: T.J. Mercier <tjmercier@google.com> +Signed-off-by: Yong Wu <yong.wu@mediatek.com> +Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/lkml/20230911023038.30649-3-yong.wu@mediatek.com/] +--- + drivers/dma-buf/dma-heap.c | 38 ++++++++++++++++++++++++++++++++++---- + include/linux/dma-heap.h | 6 ++++++ + 2 files changed, 40 insertions(+), 4 deletions(-) + +diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c +index 84ae708fafe7..59328045975a 100644 +--- a/drivers/dma-buf/dma-heap.c ++++ b/drivers/dma-buf/dma-heap.c +@@ -12,6 +12,7 @@ + #include <linux/dma-buf.h> + #include <linux/err.h> + #include <linux/xarray.h> ++#include <linux/kref.h> + #include <linux/list.h> + #include <linux/slab.h> + #include <linux/nospec.h> +@@ -31,6 +32,8 @@ + * @heap_devt heap device node + * @list list head connecting to list of heaps + * @heap_cdev heap char device ++ * @minor: heap device node minor number ++ * @refcount: reference counter for this heap device + * + * Represents a heap of memory from which buffers can be made. + */ +@@ -41,6 +44,8 @@ struct dma_heap { + dev_t heap_devt; + struct list_head list; + struct cdev heap_cdev; ++ int minor; ++ struct kref refcount; + }; + + static LIST_HEAD(heap_list); +@@ -220,7 +225,6 @@ struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + { + struct dma_heap *heap, *h, *err_ret; + struct device *dev_ret; +- unsigned int minor; + int ret; + + if (!exp_info->name || !strcmp(exp_info->name, "")) { +@@ -237,12 +241,13 @@ struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + if (!heap) + return ERR_PTR(-ENOMEM); + ++ kref_init(&heap->refcount); + heap->name = exp_info->name; + heap->ops = exp_info->ops; + heap->priv = exp_info->priv; + + /* Find unused minor number */ +- ret = xa_alloc(&dma_heap_minors, &minor, heap, ++ ret = xa_alloc(&dma_heap_minors, &heap->minor, heap, + XA_LIMIT(0, NUM_HEAP_MINORS - 1), GFP_KERNEL); + if (ret < 0) { + pr_err("dma_heap: Unable to get minor number for heap\n"); +@@ -251,7 +256,7 @@ struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + } + + /* Create device */ +- heap->heap_devt = MKDEV(MAJOR(dma_heap_devt), minor); ++ heap->heap_devt = MKDEV(MAJOR(dma_heap_devt), heap->minor); + + cdev_init(&heap->heap_cdev, &dma_heap_fops); + ret = cdev_add(&heap->heap_cdev, heap->heap_devt, 1); +@@ -295,12 +300,37 @@ struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + err2: + cdev_del(&heap->heap_cdev); + err1: +- xa_erase(&dma_heap_minors, minor); ++ xa_erase(&dma_heap_minors, heap->minor); + err0: + kfree(heap); + return err_ret; + } + ++static void dma_heap_release(struct kref *ref) ++{ ++ struct dma_heap *heap = container_of(ref, struct dma_heap, refcount); ++ ++ /* Note, we already holding the heap_list_lock here */ ++ list_del(&heap->list); ++ ++ device_destroy(dma_heap_class, heap->heap_devt); ++ cdev_del(&heap->heap_cdev); ++ xa_erase(&dma_heap_minors, heap->minor); ++ ++ kfree(heap); ++} ++ ++void dma_heap_put(struct dma_heap *h) ++{ ++ /* ++ * Take the heap_list_lock now to avoid racing with code ++ * scanning the list and then taking a kref. ++ */ ++ mutex_lock(&heap_list_lock); ++ kref_put(&h->refcount, dma_heap_release); ++ mutex_unlock(&heap_list_lock); ++} ++ + static char *dma_heap_devnode(const struct device *dev, umode_t *mode) + { + return kasprintf(GFP_KERNEL, "dma_heap/%s", dev_name(dev)); +diff --git a/include/linux/dma-heap.h b/include/linux/dma-heap.h +index 0c05561cad6e..f8c986dd9a8b 100644 +--- a/include/linux/dma-heap.h ++++ b/include/linux/dma-heap.h +@@ -65,4 +65,10 @@ const char *dma_heap_get_name(struct dma_heap *heap); + */ + struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info); + ++/** ++ * dma_heap_put - drops a reference to a dmabuf heap, potentially freeing it ++ * @heap: the heap whose reference count to decrement ++ */ ++void dma_heap_put(struct dma_heap *heap); ++ + #endif /* _DMA_HEAPS_H */ +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/0002-FROMLIST-dma-heap-Provide-accessors-so-that-in-kerne.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/0002-FROMLIST-dma-heap-Provide-accessors-so-that-in-kerne.patch new file mode 100644 index 0000000..f65b7cb --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/0002-FROMLIST-dma-heap-Provide-accessors-so-that-in-kerne.patch @@ -0,0 +1,180 @@ +From fd0d8a09c8d928459d37ae535825018bb0594357 Mon Sep 17 00:00:00 2001 +From: John Stultz <jstultz@google.com> +Date: Mon, 11 Sep 2023 10:30:32 +0800 +Subject: [PATCH 2/2] FROMLIST: dma-heap: Provide accessors so that in-kernel + drivers can allocate dmabufs from specific heaps + +This allows drivers who don't want to create their own +DMA-BUF exporter to be able to allocate DMA-BUFs directly +from existing DMA-BUF Heaps. + +There is some concern that the premise of DMA-BUF heaps is +that userland knows better about what type of heap memory +is needed for a pipeline, so it would likely be best for +drivers to import and fill DMA-BUFs allocated by userland +instead of allocating one themselves, but this is still +up for debate. + +[Yong: Fix the checkpatch alignment warning] +Signed-off-by: John Stultz <jstultz@google.com> +Signed-off-by: T.J. Mercier <tjmercier@google.com> +Signed-off-by: Yong Wu <yong.wu@mediatek.com> +Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/lkml/20230911023038.30649-4-yong.wu@mediatek.com/] +--- + drivers/dma-buf/dma-heap.c | 60 ++++++++++++++++++++++++++++---------- + include/linux/dma-heap.h | 25 ++++++++++++++++ + 2 files changed, 69 insertions(+), 16 deletions(-) + +diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c +index 59328045975a..e17705427b23 100644 +--- a/drivers/dma-buf/dma-heap.c ++++ b/drivers/dma-buf/dma-heap.c +@@ -54,12 +54,15 @@ static dev_t dma_heap_devt; + static struct class *dma_heap_class; + static DEFINE_XARRAY_ALLOC(dma_heap_minors); + +-static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, +- unsigned int fd_flags, +- unsigned int heap_flags) ++struct dma_buf *dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, ++ unsigned int fd_flags, ++ unsigned int heap_flags) + { +- struct dma_buf *dmabuf; +- int fd; ++ if (fd_flags & ~DMA_HEAP_VALID_FD_FLAGS) ++ return ERR_PTR(-EINVAL); ++ ++ if (heap_flags & ~DMA_HEAP_VALID_HEAP_FLAGS) ++ return ERR_PTR(-EINVAL); + + /* + * Allocations from all heaps have to begin +@@ -67,9 +70,20 @@ static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, + */ + len = PAGE_ALIGN(len); + if (!len) +- return -EINVAL; ++ return ERR_PTR(-EINVAL); + +- dmabuf = heap->ops->allocate(heap, len, fd_flags, heap_flags); ++ return heap->ops->allocate(heap, len, fd_flags, heap_flags); ++} ++EXPORT_SYMBOL_GPL(dma_heap_buffer_alloc); ++ ++static int dma_heap_bufferfd_alloc(struct dma_heap *heap, size_t len, ++ unsigned int fd_flags, ++ unsigned int heap_flags) ++{ ++ struct dma_buf *dmabuf; ++ int fd; ++ ++ dmabuf = dma_heap_buffer_alloc(heap, len, fd_flags, heap_flags); + if (IS_ERR(dmabuf)) + return PTR_ERR(dmabuf); + +@@ -107,15 +121,9 @@ static long dma_heap_ioctl_allocate(struct file *file, void *data) + if (heap_allocation->fd) + return -EINVAL; + +- if (heap_allocation->fd_flags & ~DMA_HEAP_VALID_FD_FLAGS) +- return -EINVAL; +- +- if (heap_allocation->heap_flags & ~DMA_HEAP_VALID_HEAP_FLAGS) +- return -EINVAL; +- +- fd = dma_heap_buffer_alloc(heap, heap_allocation->len, +- heap_allocation->fd_flags, +- heap_allocation->heap_flags); ++ fd = dma_heap_bufferfd_alloc(heap, heap_allocation->len, ++ heap_allocation->fd_flags, ++ heap_allocation->heap_flags); + if (fd < 0) + return fd; + +@@ -220,6 +228,7 @@ const char *dma_heap_get_name(struct dma_heap *heap) + { + return heap->name; + } ++EXPORT_SYMBOL_GPL(dma_heap_get_name); + + struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + { +@@ -305,6 +314,24 @@ struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) + kfree(heap); + return err_ret; + } ++EXPORT_SYMBOL_GPL(dma_heap_add); ++ ++struct dma_heap *dma_heap_find(const char *name) ++{ ++ struct dma_heap *h; ++ ++ mutex_lock(&heap_list_lock); ++ list_for_each_entry(h, &heap_list, list) { ++ if (!strcmp(h->name, name)) { ++ kref_get(&h->refcount); ++ mutex_unlock(&heap_list_lock); ++ return h; ++ } ++ } ++ mutex_unlock(&heap_list_lock); ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(dma_heap_find); + + static void dma_heap_release(struct kref *ref) + { +@@ -330,6 +357,7 @@ void dma_heap_put(struct dma_heap *h) + kref_put(&h->refcount, dma_heap_release); + mutex_unlock(&heap_list_lock); + } ++EXPORT_SYMBOL_GPL(dma_heap_put); + + static char *dma_heap_devnode(const struct device *dev, umode_t *mode) + { +diff --git a/include/linux/dma-heap.h b/include/linux/dma-heap.h +index f8c986dd9a8b..31f44d83f11b 100644 +--- a/include/linux/dma-heap.h ++++ b/include/linux/dma-heap.h +@@ -65,10 +65,35 @@ const char *dma_heap_get_name(struct dma_heap *heap); + */ + struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info); + ++/** ++ * dma_heap_find - get the heap registered with the specified name ++ * @name: Name of the DMA-Heap to find ++ * ++ * Returns: ++ * The DMA-Heap with the provided name. ++ * ++ * NOTE: DMA-Heaps returned from this function MUST be released using ++ * dma_heap_put() when the user is done to enable the heap to be unloaded. ++ */ ++struct dma_heap *dma_heap_find(const char *name); ++ + /** + * dma_heap_put - drops a reference to a dmabuf heap, potentially freeing it + * @heap: the heap whose reference count to decrement + */ + void dma_heap_put(struct dma_heap *heap); + ++/** ++ * dma_heap_buffer_alloc - Allocate dma-buf from a dma_heap ++ * @heap: DMA-Heap to allocate from ++ * @len: size to allocate in bytes ++ * @fd_flags: flags to set on returned dma-buf fd ++ * @heap_flags: flags to pass to the dma heap ++ * ++ * This is for internal dma-buf allocations only. Free returned buffers with dma_buf_put(). ++ */ ++struct dma_buf *dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, ++ unsigned int fd_flags, ++ unsigned int heap_flags); ++ + #endif /* _DMA_HEAPS_H */ +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0001-interconnect-qcom-icc-rpm-Add-AB-IB-calculations-coe.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0001-interconnect-qcom-icc-rpm-Add-AB-IB-calculations-coe.patch new file mode 100644 index 0000000..6b8e76f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0001-interconnect-qcom-icc-rpm-Add-AB-IB-calculations-coe.patch @@ -0,0 +1,97 @@ +From dd014803f260b337daaabcde259daf70d5b26b5e Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:23 +0200 +Subject: [PATCH 1/9] interconnect: qcom: icc-rpm: Add AB/IB calculations + coefficients + +Presumably due to the hardware being so complex, some nodes (or busses) +have different (usually higher) requirements for bandwidth than what +the usual calculations would suggest. + +Looking at the available downstream files, it seems like AB values are +adjusted per-bus and IB values are adjusted per-node. +With that in mind, introduce percentage-based coefficient struct members +and use them in the calculations. + +One thing to note is that the IB coefficient is inverse (100/ib_percent) +which feels a bit backwards, but it's necessary for precision.. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-1-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git dd014803f260] +--- + drivers/interconnect/qcom/icc-rpm.c | 18 +++++++++++++++--- + drivers/interconnect/qcom/icc-rpm.h | 6 ++++++ + 2 files changed, 21 insertions(+), 3 deletions(-) + +diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c +index 2c16917ba1fd..8b02aa8aa96a 100644 +--- a/drivers/interconnect/qcom/icc-rpm.c ++++ b/drivers/interconnect/qcom/icc-rpm.c +@@ -298,7 +298,8 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + */ + static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) + { +- u64 agg_avg_rate, agg_rate; ++ struct qcom_icc_provider *qp = to_qcom_provider(provider); ++ u64 agg_avg_rate, agg_peak_rate, agg_rate; + struct qcom_icc_node *qn; + struct icc_node *node; + int i; +@@ -315,8 +316,19 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r + else + agg_avg_rate = qn->sum_avg[i]; + +- agg_rate = max_t(u64, agg_avg_rate, qn->max_peak[i]); +- do_div(agg_rate, qn->buswidth); ++ if (qp->ab_coeff) { ++ agg_avg_rate = agg_avg_rate * qp->ab_coeff; ++ agg_avg_rate = div_u64(agg_avg_rate, 100); ++ } ++ ++ if (qp->ib_coeff) { ++ agg_peak_rate = qn->max_peak[i] * 100; ++ agg_peak_rate = div_u64(qn->max_peak[i], qp->ib_coeff); ++ } else { ++ agg_peak_rate = qn->max_peak[i]; ++ } ++ ++ agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); + + agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); + } +diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h +index eed3451af3e6..5e7d6a4fd2f3 100644 +--- a/drivers/interconnect/qcom/icc-rpm.h ++++ b/drivers/interconnect/qcom/icc-rpm.h +@@ -44,6 +44,8 @@ struct rpm_clk_resource { + * @type: the ICC provider type + * @regmap: regmap for QoS registers read/write access + * @qos_offset: offset to QoS registers ++ * @ab_coeff: a percentage-based coefficient for compensating the AB calculations ++ * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations + * @bus_clk_rate: bus clock rate in Hz + * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks + * @bus_clk: a pointer to a HLOS-owned bus clock +@@ -57,6 +59,8 @@ struct qcom_icc_provider { + enum qcom_icc_type type; + struct regmap *regmap; + unsigned int qos_offset; ++ u16 ab_coeff; ++ u16 ib_coeff; + u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; + const struct rpm_clk_resource *bus_clk_desc; + struct clk *bus_clk; +@@ -123,6 +127,8 @@ struct qcom_icc_desc { + enum qcom_icc_type type; + const struct regmap_config *regmap_cfg; + unsigned int qos_offset; ++ u16 ab_coeff; ++ u16 ib_coeff; + }; + + /* Valid for all bus types */ +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0002-interconnect-qcom-icc-rpm-Separate-out-clock-rate-ca.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0002-interconnect-qcom-icc-rpm-Separate-out-clock-rate-ca.patch new file mode 100644 index 0000000..be1d79f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0002-interconnect-qcom-icc-rpm-Separate-out-clock-rate-ca.patch @@ -0,0 +1,100 @@ +From db8fc1002c53bc17a3ca6fad2c524de42b77c146 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:24 +0200 +Subject: [PATCH 2/9] interconnect: qcom: icc-rpm: Separate out clock rate + calulcations + +In preparation for also setting per-node clock rates, separate out the +logic that computes it. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-2-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git db8fc1002c53] +--- + drivers/interconnect/qcom/icc-rpm.c | 53 ++++++++++++++++------------- + 1 file changed, 30 insertions(+), 23 deletions(-) + +diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c +index 8b02aa8aa96a..8c1bfd65d774 100644 +--- a/drivers/interconnect/qcom/icc-rpm.c ++++ b/drivers/interconnect/qcom/icc-rpm.c +@@ -291,6 +291,32 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + return 0; + } + ++static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node *qn, int ctx) ++{ ++ u64 agg_avg_rate, agg_peak_rate, agg_rate; ++ ++ if (qn->channels) ++ agg_avg_rate = div_u64(qn->sum_avg[ctx], qn->channels); ++ else ++ agg_avg_rate = qn->sum_avg[ctx]; ++ ++ if (qp->ab_coeff) { ++ agg_avg_rate = agg_avg_rate * qp->ab_coeff; ++ agg_avg_rate = div_u64(agg_avg_rate, 100); ++ } ++ ++ if (qp->ib_coeff) { ++ agg_peak_rate = qn->max_peak[ctx] * 100; ++ agg_peak_rate = div_u64(qn->max_peak[ctx], qp->ib_coeff); ++ } else { ++ agg_peak_rate = qn->max_peak[ctx]; ++ } ++ ++ agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); ++ ++ return div_u64(agg_rate, qn->buswidth); ++} ++ + /** + * qcom_icc_bus_aggregate - calculate bus clock rates by traversing all nodes + * @provider: generic interconnect provider +@@ -299,10 +325,9 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) + { + struct qcom_icc_provider *qp = to_qcom_provider(provider); +- u64 agg_avg_rate, agg_peak_rate, agg_rate; + struct qcom_icc_node *qn; + struct icc_node *node; +- int i; ++ int ctx; + + /* + * Iterate nodes on the provider, aggregate bandwidth requests for +@@ -310,27 +335,9 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r + */ + list_for_each_entry(node, &provider->nodes, node_list) { + qn = node->data; +- for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) { +- if (qn->channels) +- agg_avg_rate = div_u64(qn->sum_avg[i], qn->channels); +- else +- agg_avg_rate = qn->sum_avg[i]; +- +- if (qp->ab_coeff) { +- agg_avg_rate = agg_avg_rate * qp->ab_coeff; +- agg_avg_rate = div_u64(agg_avg_rate, 100); +- } +- +- if (qp->ib_coeff) { +- agg_peak_rate = qn->max_peak[i] * 100; +- agg_peak_rate = div_u64(qn->max_peak[i], qp->ib_coeff); +- } else { +- agg_peak_rate = qn->max_peak[i]; +- } +- +- agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); +- +- agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); ++ for (ctx = 0; ctx < QCOM_SMD_RPM_STATE_NUM; ctx++) { ++ agg_clk_rate[ctx] = max_t(u64, agg_clk_rate[ctx], ++ qcom_icc_calc_rate(qp, qn, ctx)); + } + } + } +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0003-interconnect-qcom-icc-rpm-Let-nodes-drive-their-own-.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0003-interconnect-qcom-icc-rpm-Let-nodes-drive-their-own-.patch new file mode 100644 index 0000000..f71cf3d --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0003-interconnect-qcom-icc-rpm-Let-nodes-drive-their-own-.patch @@ -0,0 +1,99 @@ +From 919791d82d3b878094e9edc39b0d9a4eafcc0860 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:25 +0200 +Subject: [PATCH 3/9] interconnect: qcom: icc-rpm: Let nodes drive their own + bus clock + +If this hardware couldn't get messier, some nodes are supposed to drive +their own bus clock.. Presumably to connect to some intermediate +interface between the node itself and the bus it's (supposed to be) +connected to. + +Expand the node struct with the necessary data and hook up the +allocations & calculations. + +Note that the node-specific AB/IB coefficients contribute (by design) +to both the node-level and the bus-level aggregation. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-3-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 919791d82d3b] +--- + drivers/interconnect/qcom/icc-rpm.c | 27 +++++++++++++++++++++++++++ + drivers/interconnect/qcom/icc-rpm.h | 4 ++++ + 2 files changed, 31 insertions(+) + +diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c +index 8c1bfd65d774..1d3af4e9ead8 100644 +--- a/drivers/interconnect/qcom/icc-rpm.c ++++ b/drivers/interconnect/qcom/icc-rpm.c +@@ -414,6 +414,33 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) + qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; + } + ++ /* Handle the node-specific clock */ ++ if (!src_qn->bus_clk_desc) ++ return 0; ++ ++ active_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_ACTIVE_STATE); ++ sleep_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_SLEEP_STATE); ++ ++ if (active_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) { ++ ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_ACTIVE_STATE, ++ active_rate); ++ if (ret) ++ return ret; ++ ++ /* Cache the rate after we've successfully committed it to RPM */ ++ src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate; ++ } ++ ++ if (sleep_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE]) { ++ ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_SLEEP_STATE, ++ sleep_rate); ++ if (ret) ++ return ret; ++ ++ /* Cache the rate after we've successfully committed it to RPM */ ++ src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; ++ } ++ + return 0; + } + +diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h +index 5e7d6a4fd2f3..725e0d4840e4 100644 +--- a/drivers/interconnect/qcom/icc-rpm.h ++++ b/drivers/interconnect/qcom/icc-rpm.h +@@ -97,11 +97,13 @@ struct qcom_icc_qos { + * @num_links: the total number of @links + * @channels: number of channels at this node (e.g. DDR channels) + * @buswidth: width of the interconnect between a node and the bus (bytes) ++ * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks + * @sum_avg: current sum aggregate value of all avg bw requests + * @max_peak: current max aggregate value of all peak bw requests + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @qos: NoC QoS setting parameters ++ * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz + */ + struct qcom_icc_node { + unsigned char *name; +@@ -110,11 +112,13 @@ struct qcom_icc_node { + u16 num_links; + u16 channels; + u16 buswidth; ++ const struct rpm_clk_resource *bus_clk_desc; + u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; + u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; + int mas_rpm_id; + int slv_rpm_id; + struct qcom_icc_qos qos; ++ u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; + }; + + struct qcom_icc_desc { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0004-interconnect-qcom-icc-rpm-Check-for-node-specific-ra.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0004-interconnect-qcom-icc-rpm-Check-for-node-specific-ra.patch new file mode 100644 index 0000000..faee1be --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0004-interconnect-qcom-icc-rpm-Check-for-node-specific-ra.patch @@ -0,0 +1,82 @@ +From ba3f826639782587b70a684dae79d39f6d3c433e Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:26 +0200 +Subject: [PATCH 4/9] interconnect: qcom: icc-rpm: Check for node-specific rate + coefficients + +Some nodes may have different coefficients than the general values for +bus they're attached to. Check for that and use them if present. See +[1], [2] for reference. + +[1] https://github.com/sonyxperiadev/kernel/commit/7456d9779af9ad6bb9c7ee6f33d5c5a8d3648e24 +[2] https://github.com/artem/android_kernel_sony_msm8996/commit/bf7a8985dcaf0eab5bc2562d2d6775e7e29c0f30 +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-4-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git ba3f82663978] +--- + drivers/interconnect/qcom/icc-rpm.c | 14 ++++++++++---- + drivers/interconnect/qcom/icc-rpm.h | 4 ++++ + 2 files changed, 14 insertions(+), 4 deletions(-) + +diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c +index 1d3af4e9ead8..9c40314e03b5 100644 +--- a/drivers/interconnect/qcom/icc-rpm.c ++++ b/drivers/interconnect/qcom/icc-rpm.c +@@ -300,14 +300,14 @@ static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node + else + agg_avg_rate = qn->sum_avg[ctx]; + +- if (qp->ab_coeff) { +- agg_avg_rate = agg_avg_rate * qp->ab_coeff; ++ if (qn->ab_coeff) { ++ agg_avg_rate = agg_avg_rate * qn->ab_coeff; + agg_avg_rate = div_u64(agg_avg_rate, 100); + } + +- if (qp->ib_coeff) { ++ if (qn->ib_coeff) { + agg_peak_rate = qn->max_peak[ctx] * 100; +- agg_peak_rate = div_u64(qn->max_peak[ctx], qp->ib_coeff); ++ agg_peak_rate = div_u64(qn->max_peak[ctx], qn->ib_coeff); + } else { + agg_peak_rate = qn->max_peak[ctx]; + } +@@ -563,6 +563,12 @@ int qnoc_probe(struct platform_device *pdev) + for (i = 0; i < num_nodes; i++) { + size_t j; + ++ if (!qnodes[i]->ab_coeff) ++ qnodes[i]->ab_coeff = qp->ab_coeff; ++ ++ if (!qnodes[i]->ib_coeff) ++ qnodes[i]->ib_coeff = qp->ib_coeff; ++ + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); +diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h +index 725e0d4840e4..4abf99ce2690 100644 +--- a/drivers/interconnect/qcom/icc-rpm.h ++++ b/drivers/interconnect/qcom/icc-rpm.h +@@ -103,6 +103,8 @@ struct qcom_icc_qos { + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @qos: NoC QoS setting parameters ++ * @ab_coeff: a percentage-based coefficient for compensating the AB calculations ++ * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations + * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz + */ + struct qcom_icc_node { +@@ -118,6 +120,8 @@ struct qcom_icc_node { + int mas_rpm_id; + int slv_rpm_id; + struct qcom_icc_qos qos; ++ u16 ab_coeff; ++ u16 ib_coeff; + u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; + }; + +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0005-interconnect-qcom-qcm2290-Hook-up-MAS_APPS_PROC-s-bu.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0005-interconnect-qcom-qcm2290-Hook-up-MAS_APPS_PROC-s-bu.patch new file mode 100644 index 0000000..4a0bbb4 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0005-interconnect-qcom-qcm2290-Hook-up-MAS_APPS_PROC-s-bu.patch @@ -0,0 +1,69 @@ +From fa35757ae0a5a88bd1b7df8578ee9dac9d147c64 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:27 +0200 +Subject: [PATCH 5/9] interconnect: qcom: qcm2290: Hook up MAS_APPS_PROC's bus + clock + +This single node has its own clock which seems to be responsible for +transactions between CPUSS (CPU + some stuff) and the GNOC. See [1] +for reference. + +Define it and hook it up. + +[1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/02f8c342b23c20a5cf967df649814be37a08227c%5E%21/#F0 +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-5-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git fa35757ae0a5] +--- + drivers/interconnect/qcom/icc-rpm-clocks.c | 6 ++++++ + drivers/interconnect/qcom/icc-rpm.h | 1 + + drivers/interconnect/qcom/qcm2290.c | 3 +++ + 3 files changed, 10 insertions(+) + +diff --git a/drivers/interconnect/qcom/icc-rpm-clocks.c b/drivers/interconnect/qcom/icc-rpm-clocks.c +index 63c82a91bbc7..ac1677de7dfd 100644 +--- a/drivers/interconnect/qcom/icc-rpm-clocks.c ++++ b/drivers/interconnect/qcom/icc-rpm-clocks.c +@@ -25,6 +25,12 @@ const struct rpm_clk_resource bimc_clk = { + }; + EXPORT_SYMBOL_GPL(bimc_clk); + ++const struct rpm_clk_resource mem_1_clk = { ++ .resource_type = QCOM_SMD_RPM_MEM_CLK, ++ .clock_id = 1, ++}; ++EXPORT_SYMBOL_GPL(mem_1_clk); ++ + const struct rpm_clk_resource bus_0_clk = { + .resource_type = QCOM_SMD_RPM_BUS_CLK, + .clock_id = 0, +diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h +index 4abf99ce2690..a13768cfd231 100644 +--- a/drivers/interconnect/qcom/icc-rpm.h ++++ b/drivers/interconnect/qcom/icc-rpm.h +@@ -152,6 +152,7 @@ extern const struct rpm_clk_resource bimc_clk; + extern const struct rpm_clk_resource bus_0_clk; + extern const struct rpm_clk_resource bus_1_clk; + extern const struct rpm_clk_resource bus_2_clk; ++extern const struct rpm_clk_resource mem_1_clk; + extern const struct rpm_clk_resource mmaxi_0_clk; + extern const struct rpm_clk_resource mmaxi_1_clk; + extern const struct rpm_clk_resource qup_clk; +diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c +index 5bc4b7516608..026e4c82d6d4 100644 +--- a/drivers/interconnect/qcom/qcm2290.c ++++ b/drivers/interconnect/qcom/qcm2290.c +@@ -112,6 +112,9 @@ static struct qcom_icc_node mas_appss_proc = { + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.prio_level = 0, + .qos.areq_prio = 0, ++ .bus_clk_desc = &mem_1_clk, ++ .ab_coeff = 159, ++ .ib_coeff = 96, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_appss_proc_links), +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0006-interconnect-qcom-qcm2290-Set-AB-coefficients.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0006-interconnect-qcom-qcm2290-Set-AB-coefficients.patch new file mode 100644 index 0000000..3062f49 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0006-interconnect-qcom-qcm2290-Set-AB-coefficients.patch @@ -0,0 +1,47 @@ +From 8657ed471196f4dc8e7917453a39363e0014840c Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:28 +0200 +Subject: [PATCH 6/9] interconnect: qcom: qcm2290: Set AB coefficients + +Some buses need additional manual adjustments atop the usual +calculations. Fill in the missing coefficients. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-6-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 8657ed471196] +--- + drivers/interconnect/qcom/qcm2290.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c +index 026e4c82d6d4..7abc0c449220 100644 +--- a/drivers/interconnect/qcom/qcm2290.c ++++ b/drivers/interconnect/qcom/qcm2290.c +@@ -1202,6 +1202,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { + .keep_alive = true, + /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ + .qos_offset = 0x8000, ++ .ab_coeff = 153, + }; + + static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { +@@ -1332,6 +1333,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { + .regmap_cfg = &qcm2290_snoc_regmap_config, + .keep_alive = true, + .qos_offset = 0x15000, ++ .ab_coeff = 142, + }; + + static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { +@@ -1348,6 +1350,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = { + .regmap_cfg = &qcm2290_snoc_regmap_config, + .keep_alive = true, + .qos_offset = 0x15000, ++ .ab_coeff = 139, + }; + + static const struct of_device_id qcm2290_noc_of_match[] = { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0007-interconnect-qcom-qcm2290-Update-EBI-channel-configu.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0007-interconnect-qcom-qcm2290-Update-EBI-channel-configu.patch new file mode 100644 index 0000000..c6960d8 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0007-interconnect-qcom-qcm2290-Update-EBI-channel-configu.patch @@ -0,0 +1,43 @@ +From 550064a85ba564cfb508a995f45e39a6ad0e26ed Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:29 +0200 +Subject: [PATCH 7/9] interconnect: qcom: qcm2290: Update EBI channel + configuration + +QCM2290 can support two memory configurations: single-channel, 32-bit +wide LPDDR3 @ up to 933MHz (bus clock) or dual-channel, 16-bit wide +LPDDR4X @ up to 1804 MHz. The interconnect driver in its current form +seems to gravitate towards the first one, however there are no LPDDR3- +equipped boards upstream and we still don't have a great way to discern +the DDR generations on the kernel side. + +To make DDR scaling possible on the only currently-supported 2290 +board, stick with the LPDDR4X config by default. The side effect on any +potential LPDDR3 board would be that the requested bus clock rate is +too high (but still capped to the firmware-configured FMAX). + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-7-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 550064a85ba5] +--- + drivers/interconnect/qcom/qcm2290.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c +index 7abc0c449220..b88cf9a022e0 100644 +--- a/drivers/interconnect/qcom/qcm2290.c ++++ b/drivers/interconnect/qcom/qcm2290.c +@@ -678,7 +678,8 @@ static struct qcom_icc_node mas_gfx3d = { + static struct qcom_icc_node slv_ebi1 = { + .name = "slv_ebi1", + .id = QCM2290_SLAVE_EBI1, +- .buswidth = 8, ++ .buswidth = 4, ++ .channels = 2, + .mas_rpm_id = -1, + .slv_rpm_id = 0, + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0008-interconnect-qcom-sdm660-Set-AB-IB-coefficients.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0008-interconnect-qcom-sdm660-Set-AB-IB-coefficients.patch new file mode 100644 index 0000000..af67d8c --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0008-interconnect-qcom-sdm660-Set-AB-IB-coefficients.patch @@ -0,0 +1,55 @@ +From a4a9251760185af9ca7ff1592a05a0eabfe0cd00 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:30 +0200 +Subject: [PATCH 8/9] interconnect: qcom: sdm660: Set AB/IB coefficients + +Some buses and nodes need additional manual adjustments atop the usual +calculations. Fill in the missing coefficients. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-8-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git a4a925176018] +--- + drivers/interconnect/qcom/sdm660.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c +index 36962f7bd7bb..7392bebba334 100644 +--- a/drivers/interconnect/qcom/sdm660.c ++++ b/drivers/interconnect/qcom/sdm660.c +@@ -602,6 +602,7 @@ static struct qcom_icc_node mas_mdp_p0 = { + .name = "mas_mdp_p0", + .id = SDM660_MASTER_MDP_P0, + .buswidth = 16, ++ .ib_coeff = 50, + .mas_rpm_id = 8, + .slv_rpm_id = -1, + .qos.ap_owned = true, +@@ -621,6 +622,7 @@ static struct qcom_icc_node mas_mdp_p1 = { + .name = "mas_mdp_p1", + .id = SDM660_MASTER_MDP_P1, + .buswidth = 16, ++ .ib_coeff = 50, + .mas_rpm_id = 61, + .slv_rpm_id = -1, + .qos.ap_owned = true, +@@ -1540,6 +1542,7 @@ static const struct qcom_icc_desc sdm660_bimc = { + .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), + .bus_clk_desc = &bimc_clk, + .regmap_cfg = &sdm660_bimc_regmap_config, ++ .ab_coeff = 153, + }; + + static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { +@@ -1659,6 +1662,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { + .intf_clocks = mm_intf_clocks, + .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), + .regmap_cfg = &sdm660_mnoc_regmap_config, ++ .ab_coeff = 153, + }; + + static struct qcom_icc_node * const sdm660_snoc_nodes[] = { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0009-interconnect-qcom-msm8996-Set-AB-IB-coefficients.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0009-interconnect-qcom-msm8996-Set-AB-IB-coefficients.patch new file mode 100644 index 0000000..ff49eb0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/icc/0009-interconnect-qcom-msm8996-Set-AB-IB-coefficients.patch @@ -0,0 +1,59 @@ +From 1255f23c219a74f2577c9ca5521abeb36db35d3b Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 25 Aug 2023 17:38:31 +0200 +Subject: [PATCH 9/9] interconnect: qcom: msm8996: Set AB/IB coefficients + +Some buses and nodes need additional manual adjustments atop the usual +calculations. Fill in the missing coefficients. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-9-c04b60caa467@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 1255f23c219a] +--- + drivers/interconnect/qcom/msm8996.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c +index 88683dfa468f..b73566c9b21f 100644 +--- a/drivers/interconnect/qcom/msm8996.c ++++ b/drivers/interconnect/qcom/msm8996.c +@@ -448,6 +448,7 @@ static struct qcom_icc_node mas_mdp_p0 = { + .name = "mas_mdp_p0", + .id = MSM8996_MASTER_MDP_PORT0, + .buswidth = 32, ++ .ib_coeff = 25, + .mas_rpm_id = 8, + .slv_rpm_id = -1, + .qos.ap_owned = true, +@@ -463,6 +464,7 @@ static struct qcom_icc_node mas_mdp_p1 = { + .name = "mas_mdp_p1", + .id = MSM8996_MASTER_MDP_PORT1, + .buswidth = 32, ++ .ib_coeff = 25, + .mas_rpm_id = 61, + .slv_rpm_id = -1, + .qos.ap_owned = true, +@@ -1889,7 +1891,8 @@ static const struct qcom_icc_desc msm8996_bimc = { + .nodes = bimc_nodes, + .num_nodes = ARRAY_SIZE(bimc_nodes), + .bus_clk_desc = &bimc_clk, +- .regmap_cfg = &msm8996_bimc_regmap_config ++ .regmap_cfg = &msm8996_bimc_regmap_config, ++ .ab_coeff = 154, + }; + + static struct qcom_icc_node * const cnoc_nodes[] = { +@@ -2004,7 +2007,8 @@ static const struct qcom_icc_desc msm8996_mnoc = { + .bus_clk_desc = &mmaxi_0_clk, + .intf_clocks = mm_intf_clocks, + .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), +- .regmap_cfg = &msm8996_mnoc_regmap_config ++ .regmap_cfg = &msm8996_mnoc_regmap_config, ++ .ab_coeff = 154, + }; + + static struct qcom_icc_node * const pnoc_nodes[] = { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0001_drm_msm_mdss_switch_mdss_to_use_devm_of_icc_get.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0001_drm_msm_mdss_switch_mdss_to_use_devm_of_icc_get.patch new file mode 100644 index 0000000..0620692 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0001_drm_msm_mdss_switch_mdss_to_use_devm_of_icc_get.patch @@ -0,0 +1,64 @@ +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Subject: drm/msm/mdss: switch mdss to use devm_of_icc_get() +Date: Sun, 03 Dec 2023 01:42:44 +0300 + +Stop using hand-written reset function for ICC release, use +devm_of_icc_get() instead. + +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/ded61d7dc5a0] +--- + drivers/gpu/drm/msm/msm_mdss.c | 16 ++-------------- + 1 file changed, 2 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 29bb38f0bb2c..53bc496ace99 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -50,14 +50,14 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + struct icc_path *path0; + struct icc_path *path1; + +- path0 = of_icc_get(dev, "mdp0-mem"); ++ path0 = devm_of_icc_get(dev, "mdp0-mem"); + if (IS_ERR_OR_NULL(path0)) + return PTR_ERR_OR_ZERO(path0); + + msm_mdss->path[0] = path0; + msm_mdss->num_paths = 1; + +- path1 = of_icc_get(dev, "mdp1-mem"); ++ path1 = devm_of_icc_get(dev, "mdp1-mem"); + if (!IS_ERR_OR_NULL(path1)) { + msm_mdss->path[1] = path1; + msm_mdss->num_paths++; +@@ -66,15 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + return 0; + } + +-static void msm_mdss_put_icc_path(void *data) +-{ +- struct msm_mdss *msm_mdss = data; +- int i; +- +- for (i = 0; i < msm_mdss->num_paths; i++) +- icc_put(msm_mdss->path[i]); +-} +- + static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) + { + int i; +@@ -391,9 +382,6 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 + dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); + + ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); +- if (ret) +- return ERR_PTR(ret); +- ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); + if (ret) + return ERR_PTR(ret); + +-- +2.39.2 diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_drm_msm_mdss_rename_path_references_to_mdp_path.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_drm_msm_mdss_rename_path_references_to_mdp_path.patch new file mode 100644 index 0000000..6416729 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_drm_msm_mdss_rename_path_references_to_mdp_path.patch @@ -0,0 +1,66 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: drm/msm/mdss: Rename path references to mdp_path +Date: Sun, 03 Dec 2023 01:42:45 +0300 + +The DPU1 driver needs to handle all MDPn<->DDR paths, as well as +CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are +calculated, but the latter one has static predefines spanning all SoCs. + +In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename +the path-related struct members to include "mdp_". + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/fabaf176322d] +--- + drivers/gpu/drm/msm/msm_mdss.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 53bc496ace99..e1b208fd072e 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -40,8 +40,8 @@ struct msm_mdss { + struct irq_domain *domain; + } irq_controller; + const struct msm_mdss_data *mdss_data; +- struct icc_path *path[2]; +- u32 num_paths; ++ struct icc_path *mdp_path[2]; ++ u32 num_mdp_paths; + }; + + static int msm_mdss_parse_data_bus_icc_path(struct device *dev, +@@ -54,13 +54,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + if (IS_ERR_OR_NULL(path0)) + return PTR_ERR_OR_ZERO(path0); + +- msm_mdss->path[0] = path0; +- msm_mdss->num_paths = 1; ++ msm_mdss->mdp_path[0] = path0; ++ msm_mdss->num_mdp_paths = 1; + + path1 = devm_of_icc_get(dev, "mdp1-mem"); + if (!IS_ERR_OR_NULL(path1)) { +- msm_mdss->path[1] = path1; +- msm_mdss->num_paths++; ++ msm_mdss->mdp_path[1] = path1; ++ msm_mdss->num_mdp_paths++; + } + + return 0; +@@ -70,8 +70,8 @@ static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) + { + int i; + +- for (i = 0; i < msm_mdss->num_paths; i++) +- icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); ++ for (i = 0; i < msm_mdss->num_mdp_paths; i++) ++ icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + } + + static void msm_mdss_irq(struct irq_desc *desc) +-- +2.39.2 diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_dt_bindings_display_msm_add_reg_bus_and_rotator_interconnects.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_dt_bindings_display_msm_add_reg_bus_and_rotator_interconnects.patch new file mode 100644 index 0000000..f2822ae --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0002_dt_bindings_display_msm_add_reg_bus_and_rotator_interconnects.patch @@ -0,0 +1,287 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: dt-bindings: display: msm: Add reg bus and rotator interconnects +Date: Wed, 29 Nov 2023 15:43:59 +0100 + +Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are +other connection paths: +- a path that connects rotator block to the DDR. +- a path that needs to be handled to ensure MDSS register access + functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG + interconnect. + +Describe these paths to allow using them in device trees and in the +driver. + +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/a1ed5860efd3] +--- + .../devicetree/bindings/display/msm/mdss-common.yaml | 18 ++++++++++++++---- + .../bindings/display/msm/qcom,qcm2290-mdss.yaml | 14 ++++++++++---- + .../bindings/display/msm/qcom,sc7180-mdss.yaml | 14 ++++++++++---- + .../bindings/display/msm/qcom,sc7280-mdss.yaml | 14 ++++++++++---- + .../bindings/display/msm/qcom,sm6115-mdss.yaml | 10 ++++++++++ + .../bindings/display/msm/qcom,sm6125-mdss.yaml | 8 ++++++-- + .../bindings/display/msm/qcom,sm6350-mdss.yaml | 8 ++++++-- + .../bindings/display/msm/qcom,sm6375-mdss.yaml | 8 ++++++-- + .../bindings/display/msm/qcom,sm8450-mdss.yaml | 13 ++++++++----- + 9 files changed, 80 insertions(+), 27 deletions(-) + +diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +index f69196e4cc76..c6305a6e0334 100644 +--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml ++++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +@@ -61,17 +61,27 @@ properties: + + ranges: true + ++ # This is not a perfect description, but it's impossible to discern and match ++ # the entries like we do with interconnect-names + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from mdp1 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- minItems: 1 +- items: +- - const: mdp0-mem +- - const: mdp1-mem ++ oneOf: ++ - minItems: 1 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg ++ ++ - minItems: 2 ++ items: ++ - const: mdp0-mem ++ - const: mdp1-mem ++ - const: cpu-cfg + + resets: + items: +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +index d71a8e09a798..f0cdb5422688 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +@@ -36,10 +36,14 @@ properties: + maxItems: 2 + + interconnects: +- maxItems: 1 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 1 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +@@ -98,8 +102,10 @@ examples: + interrupt-controller; + #interrupt-cells = <1>; + +- interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; +- interconnect-names = "mdp0-mem"; ++ interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>, ++ <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +index 3432a2407caa..7a0555b15ddf 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +@@ -36,10 +36,14 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 1 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 1 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +@@ -106,8 +110,10 @@ examples: + interrupt-controller; + #interrupt-cells = <1>; + +- interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; +- interconnect-names = "mdp0-mem"; ++ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, ++ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + iommus = <&apps_smmu 0x800 0x2>; + ranges; +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +index bbb727831fca..2947f27e0585 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +@@ -36,10 +36,14 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 1 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 1 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +@@ -118,8 +122,10 @@ examples: + interrupt-controller; + #interrupt-cells = <1>; + +- interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; +- interconnect-names = "mdp0-mem"; ++ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, ++ <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml +index dde5c2acead5..309de1953c88 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml +@@ -29,6 +29,16 @@ properties: + iommus: + maxItems: 2 + ++ interconnects: ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus ++ ++ interconnect-names: ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg ++ + patternProperties: + "^display-controller@[0-9a-f]+$": + type: object +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml +index 671c2c2aa896..3deb9dc81c9c 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml +@@ -35,10 +35,14 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 2 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 2 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml +index e1dcb453762e..c9ba1fae8042 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml +@@ -35,10 +35,14 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 2 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 2 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml +index b15c3950f09d..8e8a288d318c 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml +@@ -35,10 +35,14 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 2 ++ items: ++ - description: Interconnect path from mdp0 port to the data bus ++ - description: Interconnect path from CPU to the reg bus + + interconnect-names: +- maxItems: 2 ++ items: ++ - const: mdp0-mem ++ - const: cpu-cfg + + patternProperties: + "^display-controller@[0-9a-f]+$": +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +index 001b26e65301..747a2e9665f4 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +@@ -30,10 +30,10 @@ properties: + maxItems: 1 + + interconnects: +- maxItems: 2 ++ maxItems: 3 + + interconnect-names: +- maxItems: 2 ++ maxItems: 3 + + patternProperties: + "^display-controller@[0-9a-f]+$": +@@ -91,9 +91,12 @@ examples: + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + +- interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, +- <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; +- interconnect-names = "mdp0-mem", "mdp1-mem"; ++ interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, ++ <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, ++ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; ++ interconnect-names = "mdp0-mem", ++ "mdp1-mem", ++ "cpu-cfg"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0003_drm_msm_mdss_inline_msm_mdss_icc_request_bw.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0003_drm_msm_mdss_inline_msm_mdss_icc_request_bw.patch new file mode 100644 index 0000000..5e430b1 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0003_drm_msm_mdss_inline_msm_mdss_icc_request_bw.patch @@ -0,0 +1,69 @@ +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Subject: drm/msm/mdss: inline msm_mdss_icc_request_bw() +Date: Sun, 03 Dec 2023 01:42:46 +0300 + +There are just two places where we set the bandwidth: in the resume and +in the suspend paths. Drop the wrapping function +msm_mdss_icc_request_bw() and call icc_set_bw() directly. + +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/7323694e118a] +--- + drivers/gpu/drm/msm/msm_mdss.c | 19 ++++++++----------- + 1 file changed, 8 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index e1b208fd072e..eeca281e9d6d 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -66,14 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + return 0; + } + +-static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) +-{ +- int i; +- +- for (i = 0; i < msm_mdss->num_mdp_paths; i++) +- icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); +-} +- + static void msm_mdss_irq(struct irq_desc *desc) + { + struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); +@@ -227,14 +219,15 @@ const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) + + static int msm_mdss_enable(struct msm_mdss *msm_mdss) + { +- int ret; ++ int ret, i; + + /* + * Several components have AXI clocks that can only be turned on if + * the interconnect is enabled (non-zero bandwidth). Let's make sure + * that the interconnects are at least at a minimum amount. + */ +- msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); ++ for (i = 0; i < msm_mdss->num_mdp_paths; i++) ++ icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); + + ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); + if (ret) { +@@ -286,8 +279,12 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) + + static int msm_mdss_disable(struct msm_mdss *msm_mdss) + { ++ int i; ++ + clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); +- msm_mdss_icc_request_bw(msm_mdss, 0); ++ ++ for (i = 0; i < msm_mdss->num_mdp_paths; i++) ++ icc_set_bw(msm_mdss->mdp_path[i], 0, 0); + + return 0; + } +-- +2.39.2 diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0004_drm_msm_mdss_handle_the_reg_bus_icc_path.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0004_drm_msm_mdss_handle_the_reg_bus_icc_path.patch new file mode 100644 index 0000000..87a4b37 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mdss-icc/0004_drm_msm_mdss_handle_the_reg_bus_icc_path.patch @@ -0,0 +1,238 @@ +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Subject: drm/msm/mdss: Handle the reg bus ICC path +Date: Sun, 03 Dec 2023 01:42:47 +0300 + +Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's +another path that needs to be handled to ensure MDSS functions properly, +namely the "reg bus", a.k.a the CPU-MDSS interconnect. + +Gating that path may have a variety of effects, from none to otherwise +inexplicable DSI timeouts. + +Provide a way for MDSS driver to vote on this bus. + +A note regarding vote values. Newer platforms have corresponding +bandwidth values in the vendor DT files. For the older platforms there +was a static vote in the mdss_mdp and rotator drivers. I choose to be +conservative here and choose this value as a default. + +Co-developed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/a55c8ff252d3] +--- + drivers/gpu/drm/msm/msm_mdss.c | 49 +++++++++++++++++++++++++++++++--- + drivers/gpu/drm/msm/msm_mdss.h | 1 + + 2 files changed, 46 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index eeca281e9d6d..18b07619d6fc 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -28,6 +28,8 @@ + + #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ + ++#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ ++ + struct msm_mdss { + struct device *dev; + +@@ -42,6 +44,7 @@ struct msm_mdss { + const struct msm_mdss_data *mdss_data; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; ++ struct icc_path *reg_bus_path; + }; + + static int msm_mdss_parse_data_bus_icc_path(struct device *dev, +@@ -49,6 +52,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + { + struct icc_path *path0; + struct icc_path *path1; ++ struct icc_path *reg_bus_path; + + path0 = devm_of_icc_get(dev, "mdp0-mem"); + if (IS_ERR_OR_NULL(path0)) +@@ -63,6 +67,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, + msm_mdss->num_mdp_paths++; + } + ++ reg_bus_path = of_icc_get(dev, "cpu-cfg"); ++ if (!IS_ERR_OR_NULL(reg_bus_path)) ++ msm_mdss->reg_bus_path = reg_bus_path; ++ + return 0; + } + +@@ -229,6 +237,13 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); + ++ if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) ++ icc_set_bw(msm_mdss->reg_bus_path, 0, ++ msm_mdss->mdss_data->reg_bus_bw); ++ else ++ icc_set_bw(msm_mdss->reg_bus_path, 0, ++ DEFAULT_REG_BW); ++ + ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); + if (ret) { + dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); +@@ -286,6 +301,9 @@ static int msm_mdss_disable(struct msm_mdss *msm_mdss) + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, 0); + ++ if (msm_mdss->reg_bus_path) ++ icc_set_bw(msm_mdss->reg_bus_path, 0, 0); ++ + return 0; + } + +@@ -372,6 +390,8 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 + if (!msm_mdss) + return ERR_PTR(-ENOMEM); + ++ msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); ++ + msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); + if (IS_ERR(msm_mdss->mmio)) + return ERR_CAST(msm_mdss->mmio); +@@ -462,8 +482,6 @@ static int mdss_probe(struct platform_device *pdev) + if (IS_ERR(mdss)) + return PTR_ERR(mdss); + +- mdss->mdss_data = of_device_get_match_data(&pdev->dev); +- + platform_set_drvdata(pdev, mdss); + + /* +@@ -495,11 +513,13 @@ static const struct msm_mdss_data msm8998_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_1_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data qcm2290_data = { + /* no UBWC */ + .highest_bank_bit = 0x2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc7180_data = { +@@ -507,6 +527,7 @@ static const struct msm_mdss_data sc7180_data = { + .ubwc_dec_version = UBWC_2_0, + .ubwc_static = 0x1e, + .highest_bank_bit = 0x3, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc7280_data = { +@@ -516,6 +537,7 @@ static const struct msm_mdss_data sc7280_data = { + .ubwc_static = 1, + .highest_bank_bit = 1, + .macrotile_mode = 1, ++ .reg_bus_bw = 74000, + }; + + static const struct msm_mdss_data sc8180x_data = { +@@ -523,6 +545,7 @@ static const struct msm_mdss_data sc8180x_data = { + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sc8280xp_data = { +@@ -532,12 +555,14 @@ static const struct msm_mdss_data sc8280xp_data = { + .ubwc_static = 1, + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sdm845_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6350_data = { +@@ -546,12 +571,14 @@ static const struct msm_mdss_data sm6350_data = { + .ubwc_swizzle = 6, + .ubwc_static = 0x1e, + .highest_bank_bit = 1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm8150_data = { + .ubwc_enc_version = UBWC_3_0, + .ubwc_dec_version = UBWC_3_0, + .highest_bank_bit = 2, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6115_data = { +@@ -560,6 +587,7 @@ static const struct msm_mdss_data sm6115_data = { + .ubwc_swizzle = 7, + .ubwc_static = 0x11f, + .highest_bank_bit = 0x1, ++ .reg_bus_bw = 76800, + }; + + static const struct msm_mdss_data sm6125_data = { +@@ -577,6 +605,18 @@ static const struct msm_mdss_data sm8250_data = { + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 76800, ++}; ++ ++static const struct msm_mdss_data sm8350_data = { ++ .ubwc_enc_version = UBWC_4_0, ++ .ubwc_dec_version = UBWC_4_0, ++ .ubwc_swizzle = 6, ++ .ubwc_static = 1, ++ /* TODO: highest_bank_bit = 2 for LP_DDR4 */ ++ .highest_bank_bit = 3, ++ .macrotile_mode = 1, ++ .reg_bus_bw = 74000, + }; + + static const struct msm_mdss_data sm8550_data = { +@@ -587,6 +627,7 @@ static const struct msm_mdss_data sm8550_data = { + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, ++ .reg_bus_bw = 57000, + }; + static const struct of_device_id mdss_dt_match[] = { + { .compatible = "qcom,mdss" }, +@@ -603,8 +644,8 @@ static const struct of_device_id mdss_dt_match[] = { + { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, + { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, + { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, +- { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, +- { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, ++ { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, ++ { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, + { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, + {} + }; +diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h +index 02bbab42adbc..3afef4b1786d 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.h ++++ b/drivers/gpu/drm/msm/msm_mdss.h +@@ -14,6 +14,7 @@ struct msm_mdss_data { + u32 ubwc_static; + u32 highest_bank_bit; + u32 macrotile_mode; ++ u32 reg_bus_bw; + }; + + #define UBWC_1_0 0x10000000 +-- +2.39.2 diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0001-dt-bindings-interrupt-controller-mpm-Pass-MSG-RAM-sl.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0001-dt-bindings-interrupt-controller-mpm-Pass-MSG-RAM-sl.patch new file mode 100644 index 0000000..4614771 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0001-dt-bindings-interrupt-controller-mpm-Pass-MSG-RAM-sl.patch @@ -0,0 +1,72 @@ +From d974d3afa058b6857c95e860493542807d4a2eec Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Wed, 5 Apr 2023 12:48:34 +0200 +Subject: [PATCH 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM + slice through phandle + +Due to the wild nature of the Qualcomm RPM Message RAM, we can't really +use 'reg' to point to the MPM's slice of Message RAM without cutting into +an already-defined RPM MSG RAM node used for GLINK and SMEM. + +Document passing the register space as a slice of SRAM through the +qcom,rpm-msg-ram property. This also makes 'reg' deprecated. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git d974d3afa058] +--- + .../bindings/interrupt-controller/qcom,mpm.yaml | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +index 6a206111d4e0..ec957949a440 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +@@ -29,6 +29,12 @@ properties: + maxItems: 1 + description: + Specifies the base address and size of vMPM registers in RPM MSG RAM. ++ deprecated: true ++ ++ qcom,rpm-msg-ram: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the APSS MPM slice of the RPM Message RAM + + interrupts: + maxItems: 1 +@@ -67,23 +73,22 @@ properties: + + required: + - compatible +- - reg + - interrupts + - mboxes + - interrupt-controller + - '#interrupt-cells' + - qcom,mpm-pin-count + - qcom,mpm-pin-map ++ - qcom,rpm-msg-ram + + additionalProperties: false + + examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> +- mpm: interrupt-controller@45f01b8 { ++ mpm: interrupt-controller { + compatible = "qcom,mpm"; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; +- reg = <0x45f01b8 0x1000>; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; +@@ -96,5 +101,6 @@ examples: + <86 183>, + <90 260>, + <91 260>; ++ qcom,rpm-msg-ram = <&apss_mpm>; + #power-domain-cells = <0>; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0002-irqchip-irq-qcom-mpm-Support-passing-a-slice-of-SRAM.patch b/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0002-irqchip-irq-qcom-mpm-Support-passing-a-slice-of-SRAM.patch new file mode 100644 index 0000000..bb9a7c3 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/generic-drivers/mpm/0002-irqchip-irq-qcom-mpm-Support-passing-a-slice-of-SRAM.patch @@ -0,0 +1,78 @@ +From 24ac56bf8085adf448b6db9574d9b16ed5cd6c0b Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Wed, 5 Apr 2023 12:48:35 +0200 +Subject: [PATCH 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as + reg space + +The MPM hardware is accessible to us from the ARM CPUs through a shared +memory region (RPM MSG RAM) that's also concurrently accessed by other +kinds of cores on the system (like modem, ADSP etc.). Modeling this +relation in a (somewhat) sane manner in the device tree basically +requires us to either present the MPM as a child of said memory region +(which makes little sense, as a mapped memory carveout is not a bus), +define nodes which bleed their register spaces into one another, or +passing their slice of the MSG RAM through some kind of a property. + +Go with the third option and add a way to map a region passed through +the "qcom,rpm-msg-ram" property as our register space. + +The current way of using 'reg' is preserved for ABI reasons. + +Acked-by: Shawn Guo <shawn.guo@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 24ac56bf8085] +--- + drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c +index 7124565234a5..7115e3056aa5 100644 +--- a/drivers/irqchip/irq-qcom-mpm.c ++++ b/drivers/irqchip/irq-qcom-mpm.c +@@ -14,6 +14,7 @@ + #include <linux/mailbox_client.h> + #include <linux/module.h> + #include <linux/of.h> ++#include <linux/of_address.h> + #include <linux/of_platform.h> + #include <linux/platform_device.h> + #include <linux/pm_domain.h> +@@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) + struct device *dev = &pdev->dev; + struct irq_domain *parent_domain; + struct generic_pm_domain *genpd; ++ struct device_node *msgram_np; + struct qcom_mpm_priv *priv; + unsigned int pin_cnt; ++ struct resource res; + int i, irq; + int ret; + +@@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) + + raw_spin_lock_init(&priv->lock); + +- priv->base = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(priv->base)) +- return PTR_ERR(priv->base); ++ /* If we have a handle to an RPM message ram partition, use it. */ ++ msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); ++ if (msgram_np) { ++ ret = of_address_to_resource(msgram_np, 0, &res); ++ /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ ++ priv->base = devm_ioremap(dev, res.start, resource_size(&res)); ++ of_node_put(msgram_np); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ } else { ++ /* Otherwise, fall back to simple MMIO. */ ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ } + + for (i = 0; i < priv->reg_stride; i++) { + qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-driver/0001-dt-bindings-mfd-qcom-qca639x-add-binding-for-QCA639x.patch b/recipes-kernel/linux/linux-yocto/qca6390-driver/0001-dt-bindings-mfd-qcom-qca639x-add-binding-for-QCA639x.patch new file mode 100644 index 0000000..a9881f0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-driver/0001-dt-bindings-mfd-qcom-qca639x-add-binding-for-QCA639x.patch @@ -0,0 +1,111 @@ +From 3b909d078f454238bb9e8ec454a891765df968f6 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sun, 20 Dec 2020 18:47:57 +0300 +Subject: [PATCH 1/5] dt-bindings: mfd: qcom,qca639x: add binding for QCA639x + defvice + +Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part +being controlled through the UART and WiFi being present on PCIe bus. +Both blocks share common power sources. Add binding to describe power +sequencing required to power up this device. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + .../devicetree/bindings/mfd/qcom,qca639x.yaml | 84 +++++++++++++++++++ + 1 file changed, 84 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml + +diff --git a/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml b/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml +new file mode 100644 +index 000000000000..d43c75da136f +--- /dev/null ++++ b/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml +@@ -0,0 +1,84 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/mfd/qcom,qca639x.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: Qualcomm QCA639x WiFi + Bluetoot SoC bindings ++ ++maintainers: ++ - Andy Gross <agross@kernel.org> ++ - Bjorn Andersson <bjorn.andersson@linaro.org> ++ ++description: | ++ This binding describes thes Qualcomm QCA6390 or QCA6391 power supplies and ++ enablement pins. ++ ++properties: ++ compatible: ++ const: qcom,qca639x ++ ++ '#power-domain-cells': ++ const: 0 ++ ++ pinctrl-0: true ++ pinctrl-1: true ++ ++ pinctrl-names: ++ items: ++ - const: default ++ - const: active ++ ++ vddaon-supply: ++ description: ++ 0.95V always-on LDO power input ++ ++ vddpmu-supply: ++ description: ++ 0.95V LDO power input to PMU ++ ++ vddrfa1-supply: ++ description: ++ 0.95V LDO power input to RFA ++ ++ vddrfa2-supply: ++ description: ++ 1.25V LDO power input to RFA ++ ++ vddrfa3-supply: ++ description: ++ 2V LDO power input to RFA ++ ++ vddpcie1-supply: ++ description: ++ 1.25V LDO power input to PCIe part ++ ++ vddpcie2-supply: ++ description: ++ 2V LDO power input to PCIe part ++ ++ vddio-supply: ++ description: ++ 1.8V VIO input ++ ++additionalProperties: false ++ ++examples: ++ - | ++ qca639x: qca639x { ++ compatible = "qcom,qca639x"; ++ #power-domain-cells = <0>; ++ ++ vddaon-supply = <&vreg_s6a_0p95>; ++ vddpmu-supply = <&vreg_s2f_0p95>; ++ vddrfa1-supply = <&vreg_s2f_0p95>; ++ vddrfa2-supply = <&vreg_s8c_1p3>; ++ vddrfa3-supply = <&vreg_s5a_1p9>; ++ vddpcie1-supply = <&vreg_s8c_1p3>; ++ vddpcie2-supply = <&vreg_s5a_1p9>; ++ vddio-supply = <&vreg_s4a_1p8>; ++ pinctrl-names = "default", "active"; ++ pinctrl-0 = <&wlan_default_state &bt_default_state>; ++ pinctrl-1 = <&wlan_active_state &bt_active_state>; ++ }; ++... +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-driver/0002-mfd-qca639x-add-support-for-QCA639x-powerup-sequence.patch b/recipes-kernel/linux/linux-yocto/qca6390-driver/0002-mfd-qca639x-add-support-for-QCA639x-powerup-sequence.patch new file mode 100644 index 0000000..2621853 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-driver/0002-mfd-qca639x-add-support-for-QCA639x-powerup-sequence.patch @@ -0,0 +1,225 @@ +From 6cca247e22ac57fcc99241fee201056c1967278e Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Fri, 18 Dec 2020 16:24:56 +0300 +Subject: [PATCH 2/5] mfd: qca639x: add support for QCA639x powerup sequence + +Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part +being controlled through the UART and WiFi being present on PCIe +bus. Both blocks share common power sources. So add mfd device driver +handling power sequencing of QCA6390/1. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + drivers/mfd/Kconfig | 12 +++ + drivers/mfd/Makefile | 1 + + drivers/mfd/qcom-qca639x.c | 162 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 175 insertions(+) + create mode 100644 drivers/mfd/qcom-qca639x.c + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index e90463c4441c..9abb4df8d66b 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1086,6 +1086,18 @@ config MFD_PM8XXX + Say M here if you want to include support for PM8xxx chips as a + module. This will build a module called "pm8xxx-core". + ++config MFD_QCOM_QCA639X ++ tristate "Qualcomm QCA639x WiFi/Bluetooth module support" ++ depends on REGULATOR && PM_GENERIC_DOMAINS ++ help ++ If you say yes to this option, support will be included for Qualcomm ++ QCA639x family of WiFi and Bluetooth SoCs. Note, this driver supports ++ only power control for this SoC, you still have to enable individual ++ Bluetooth and WiFi drivers. ++ ++ Say M here if you want to include support for QCA639x chips as a ++ module. This will build a module called "qcom-qca639x". ++ + config MFD_QCOM_RPM + tristate "Qualcomm Resource Power Manager (RPM)" + depends on ARCH_QCOM && OF +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 1d2392f06f78..f7f25ef9e17a 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -197,6 +197,7 @@ obj-$(CONFIG_MFD_SI476X_CORE) += si476x-core.o + obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o + obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o + obj-$(CONFIG_MFD_PM8XXX) += qcom-pm8xxx.o ssbi.o ++obj-$(CONFIG_MFD_QCOM_QCA639X) += qcom-qca639x.o + obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o + obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o + obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o +diff --git a/drivers/mfd/qcom-qca639x.c b/drivers/mfd/qcom-qca639x.c +new file mode 100644 +index 000000000000..b31e4b65bec5 +--- /dev/null ++++ b/drivers/mfd/qcom-qca639x.c +@@ -0,0 +1,162 @@ ++#include <linux/delay.h> ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/pinctrl/consumer.h> ++#include <linux/pinctrl/devinfo.h> ++#include <linux/platform_device.h> ++#include <linux/pm_domain.h> ++#include <linux/regulator/consumer.h> ++#include <linux/slab.h> ++ ++#define MAX_NUM_REGULATORS 8 ++ ++static struct vreg { ++ const char *name; ++ unsigned int load_uA; ++} vregs [MAX_NUM_REGULATORS] = { ++ /* 2.0 V */ ++ { "vddpcie2", 15000 }, ++ { "vddrfa3", 400000 }, ++ ++ /* 0.95 V */ ++ { "vddaon", 100000 }, ++ { "vddpmu", 1250000 }, ++ { "vddrfa1", 200000 }, ++ ++ /* 1.35 V */ ++ { "vddrfa2", 400000 }, ++ { "vddpcie1", 35000 }, ++ ++ /* 1.8 V */ ++ { "vddio", 20000 }, ++}; ++ ++struct qca639x_data { ++ struct regulator_bulk_data regulators[MAX_NUM_REGULATORS]; ++ size_t num_vregs; ++ struct device *dev; ++ struct pinctrl_state *active_state; ++ struct generic_pm_domain pd; ++}; ++ ++#define domain_to_data(domain) container_of(domain, struct qca639x_data, pd) ++ ++static int qca639x_power_on(struct generic_pm_domain *domain) ++{ ++ struct qca639x_data *data = domain_to_data(domain); ++ int ret; ++ ++ dev_warn(&domain->dev, "DUMMY POWER ON\n"); ++ ++ ret = regulator_bulk_enable(data->num_vregs, data->regulators); ++ if (ret) { ++ dev_err(data->dev, "Failed to enable regulators"); ++ return ret; ++ } ++ ++ /* Wait for 1ms before toggling enable pins. */ ++ msleep(1); ++ ++ ret = pinctrl_select_state(data->dev->pins->p, data->active_state); ++ if (ret) { ++ dev_err(data->dev, "Failed to select active state"); ++ return ret; ++ } ++ ++ /* Wait for all power levels to stabilize */ ++ msleep(6); ++ ++ return 0; ++} ++ ++static int qca639x_power_off(struct generic_pm_domain *domain) ++{ ++ struct qca639x_data *data = domain_to_data(domain); ++ ++ dev_warn(&domain->dev, "DUMMY POWER OFF\n"); ++ ++ pinctrl_select_default_state(data->dev); ++ regulator_bulk_disable(data->num_vregs, data->regulators); ++ ++ return 0; ++} ++ ++static int qca639x_probe(struct platform_device *pdev) ++{ ++ struct qca639x_data *data; ++ struct device *dev = &pdev->dev; ++ int i, ret; ++ ++ if (!dev->pins || IS_ERR_OR_NULL(dev->pins->default_state)) ++ return -EINVAL; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ data->dev = dev; ++ data->num_vregs = ARRAY_SIZE(vregs); ++ ++ data->active_state = pinctrl_lookup_state(dev->pins->p, "active"); ++ if (IS_ERR(data->active_state)) { ++ ret = PTR_ERR(data->active_state); ++ dev_err(dev, "Failed to get active_state: %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < data->num_vregs; i++) ++ data->regulators[i].supply = vregs[i].name; ++ ret = devm_regulator_bulk_get(dev, data->num_vregs, data->regulators); ++ if (ret < 0) ++ return ret; ++ ++ for (i = 0; i < data->num_vregs; i++) { ++ ret = regulator_set_load(data->regulators[i].consumer, vregs[i].load_uA); ++ if (ret) ++ return ret; ++ } ++ ++ data->pd.name = dev_name(dev); ++ data->pd.power_on = qca639x_power_on; ++ data->pd.power_off = qca639x_power_off; ++ ++ ret = pm_genpd_init(&data->pd, NULL, true); ++ if (ret < 0) ++ return ret; ++ ++ ret = of_genpd_add_provider_simple(dev->of_node, &data->pd); ++ if (ret < 0) { ++ pm_genpd_remove(&data->pd); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, data); ++ ++ return 0; ++} ++ ++static int qca639x_remove(struct platform_device *pdev) ++{ ++ struct qca639x_data *data = platform_get_drvdata(pdev); ++ ++ pm_genpd_remove(&data->pd); ++ ++ return 0; ++} ++ ++static const struct of_device_id qca639x_of_match[] = { ++ { .compatible = "qcom,qca639x" }, ++}; ++ ++static struct platform_driver qca639x_driver = { ++ .probe = qca639x_probe, ++ .remove = qca639x_remove, ++ .driver = { ++ .name = "qca639x", ++ .of_match_table = qca639x_of_match, ++ }, ++}; ++ ++module_platform_driver(qca639x_driver); ++MODULE_LICENSE("GPL v2"); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-driver/0003-mfd-qcom-qca639x-switch-to-platform-config-data.patch b/recipes-kernel/linux/linux-yocto/qca6390-driver/0003-mfd-qcom-qca639x-switch-to-platform-config-data.patch new file mode 100644 index 0000000..72458ef --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-driver/0003-mfd-qcom-qca639x-switch-to-platform-config-data.patch @@ -0,0 +1,189 @@ +From bf19679f9a583a5bfd0cb711984fbe456af652fd Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sat, 26 Feb 2022 21:13:18 +0300 +Subject: [PATCH 3/5] mfd: qcom-qca639x: switch to platform config data + +Change qcom-qca639x to use platform config data, in preparation to +supporting other devices. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + drivers/mfd/qcom-qca639x.c | 74 +++++++++++++++++++++++--------------- + 1 file changed, 46 insertions(+), 28 deletions(-) + +diff --git a/drivers/mfd/qcom-qca639x.c b/drivers/mfd/qcom-qca639x.c +index b31e4b65bec5..22792561dbad 100644 +--- a/drivers/mfd/qcom-qca639x.c ++++ b/drivers/mfd/qcom-qca639x.c +@@ -1,4 +1,5 @@ + #include <linux/delay.h> ++#include <linux/gpio/consumer.h> + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/module.h> +@@ -6,15 +7,21 @@ + #include <linux/pinctrl/devinfo.h> + #include <linux/platform_device.h> + #include <linux/pm_domain.h> ++#include <linux/property.h> + #include <linux/regulator/consumer.h> + #include <linux/slab.h> + +-#define MAX_NUM_REGULATORS 8 +- +-static struct vreg { ++struct vreg { + const char *name; + unsigned int load_uA; +-} vregs [MAX_NUM_REGULATORS] = { ++}; ++ ++struct qca_cfg_data { ++ const struct vreg *vregs; ++ size_t num_vregs; ++}; ++ ++static const struct vreg qca6390_vregs[] = { + /* 2.0 V */ + { "vddpcie2", 15000 }, + { "vddrfa3", 400000 }, +@@ -32,19 +39,24 @@ static struct vreg { + { "vddio", 20000 }, + }; + +-struct qca639x_data { +- struct regulator_bulk_data regulators[MAX_NUM_REGULATORS]; ++static const struct qca_cfg_data qca6390_cfg_data = { ++ .vregs = qca6390_vregs, ++ .num_vregs = ARRAY_SIZE(qca6390_vregs), ++}; ++ ++struct qca_data { + size_t num_vregs; + struct device *dev; + struct pinctrl_state *active_state; + struct generic_pm_domain pd; ++ struct regulator_bulk_data regulators[]; + }; + +-#define domain_to_data(domain) container_of(domain, struct qca639x_data, pd) ++#define domain_to_data(domain) container_of(domain, struct qca_data, pd) + +-static int qca639x_power_on(struct generic_pm_domain *domain) ++static int qca_power_on(struct generic_pm_domain *domain) + { +- struct qca639x_data *data = domain_to_data(domain); ++ struct qca_data *data = domain_to_data(domain); + int ret; + + dev_warn(&domain->dev, "DUMMY POWER ON\n"); +@@ -70,9 +82,9 @@ static int qca639x_power_on(struct generic_pm_domain *domain) + return 0; + } + +-static int qca639x_power_off(struct generic_pm_domain *domain) ++static int qca_power_off(struct generic_pm_domain *domain) + { +- struct qca639x_data *data = domain_to_data(domain); ++ struct qca_data *data = domain_to_data(domain); + + dev_warn(&domain->dev, "DUMMY POWER OFF\n"); + +@@ -82,21 +94,26 @@ static int qca639x_power_off(struct generic_pm_domain *domain) + return 0; + } + +-static int qca639x_probe(struct platform_device *pdev) ++static int qca_probe(struct platform_device *pdev) + { +- struct qca639x_data *data; ++ const struct qca_cfg_data *cfg; ++ struct qca_data *data; + struct device *dev = &pdev->dev; + int i, ret; + ++ cfg = device_get_match_data(&pdev->dev); ++ if (!cfg) ++ return -EINVAL; ++ + if (!dev->pins || IS_ERR_OR_NULL(dev->pins->default_state)) + return -EINVAL; + +- data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ data = devm_kzalloc(dev, struct_size(data, regulators, cfg->num_vregs), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->dev = dev; +- data->num_vregs = ARRAY_SIZE(vregs); ++ data->num_vregs = cfg->num_vregs; + + data->active_state = pinctrl_lookup_state(dev->pins->p, "active"); + if (IS_ERR(data->active_state)) { +@@ -106,20 +123,20 @@ static int qca639x_probe(struct platform_device *pdev) + } + + for (i = 0; i < data->num_vregs; i++) +- data->regulators[i].supply = vregs[i].name; ++ data->regulators[i].supply = cfg->vregs[i].name; + ret = devm_regulator_bulk_get(dev, data->num_vregs, data->regulators); + if (ret < 0) + return ret; + + for (i = 0; i < data->num_vregs; i++) { +- ret = regulator_set_load(data->regulators[i].consumer, vregs[i].load_uA); ++ ret = regulator_set_load(data->regulators[i].consumer, cfg->vregs[i].load_uA); + if (ret) + return ret; + } + + data->pd.name = dev_name(dev); +- data->pd.power_on = qca639x_power_on; +- data->pd.power_off = qca639x_power_off; ++ data->pd.power_on = qca_power_on; ++ data->pd.power_off = qca_power_off; + + ret = pm_genpd_init(&data->pd, NULL, true); + if (ret < 0) +@@ -136,27 +153,28 @@ static int qca639x_probe(struct platform_device *pdev) + return 0; + } + +-static int qca639x_remove(struct platform_device *pdev) ++static int qca_remove(struct platform_device *pdev) + { +- struct qca639x_data *data = platform_get_drvdata(pdev); ++ struct qca_data *data = platform_get_drvdata(pdev); + + pm_genpd_remove(&data->pd); + + return 0; + } + +-static const struct of_device_id qca639x_of_match[] = { +- { .compatible = "qcom,qca639x" }, ++static const struct of_device_id qca_of_match[] = { ++ { .compatible = "qcom,qca6390", .data = &qca6390_cfg_data }, ++ { }, + }; + +-static struct platform_driver qca639x_driver = { +- .probe = qca639x_probe, +- .remove = qca639x_remove, ++static struct platform_driver qca_driver = { ++ .probe = qca_probe, ++ .remove = qca_remove, + .driver = { + .name = "qca639x", +- .of_match_table = qca639x_of_match, ++ .of_match_table = qca_of_match, + }, + }; + +-module_platform_driver(qca639x_driver); ++module_platform_driver(qca_driver); + MODULE_LICENSE("GPL v2"); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-driver/0004-mfd-qcom-qca639x-change-qca639x-to-use-gpios-rather-.patch b/recipes-kernel/linux/linux-yocto/qca6390-driver/0004-mfd-qcom-qca639x-change-qca639x-to-use-gpios-rather-.patch new file mode 100644 index 0000000..4520e37 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-driver/0004-mfd-qcom-qca639x-change-qca639x-to-use-gpios-rather-.patch @@ -0,0 +1,90 @@ +From 3f07b11f1bf49c153df0248de9128ffdad0792f8 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sat, 26 Feb 2022 21:17:22 +0300 +Subject: [PATCH 4/5] mfd: qcom-qca639x: change qca639x to use gpios rather + than pinctrl + +Use gpio interface instead of pinctrl interface to toggle enable pins. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + drivers/mfd/qcom-qca639x.c | 33 +++++++++++++++++++-------------- + 1 file changed, 19 insertions(+), 14 deletions(-) + +diff --git a/drivers/mfd/qcom-qca639x.c b/drivers/mfd/qcom-qca639x.c +index 22792561dbad..4de860e9bbd0 100644 +--- a/drivers/mfd/qcom-qca639x.c ++++ b/drivers/mfd/qcom-qca639x.c +@@ -47,8 +47,9 @@ static const struct qca_cfg_data qca6390_cfg_data = { + struct qca_data { + size_t num_vregs; + struct device *dev; +- struct pinctrl_state *active_state; + struct generic_pm_domain pd; ++ struct gpio_desc *wlan_en_gpio; ++ struct gpio_desc *bt_en_gpio; + struct regulator_bulk_data regulators[]; + }; + +@@ -70,11 +71,10 @@ static int qca_power_on(struct generic_pm_domain *domain) + /* Wait for 1ms before toggling enable pins. */ + msleep(1); + +- ret = pinctrl_select_state(data->dev->pins->p, data->active_state); +- if (ret) { +- dev_err(data->dev, "Failed to select active state"); +- return ret; +- } ++ if (data->wlan_en_gpio) ++ gpiod_set_value(data->wlan_en_gpio, 1); ++ if (data->bt_en_gpio) ++ gpiod_set_value(data->bt_en_gpio, 1); + + /* Wait for all power levels to stabilize */ + msleep(6); +@@ -88,7 +88,11 @@ static int qca_power_off(struct generic_pm_domain *domain) + + dev_warn(&domain->dev, "DUMMY POWER OFF\n"); + +- pinctrl_select_default_state(data->dev); ++ if (data->wlan_en_gpio) ++ gpiod_set_value(data->wlan_en_gpio, 0); ++ if (data->bt_en_gpio) ++ gpiod_set_value(data->bt_en_gpio, 0); ++ + regulator_bulk_disable(data->num_vregs, data->regulators); + + return 0; +@@ -115,13 +119,6 @@ static int qca_probe(struct platform_device *pdev) + data->dev = dev; + data->num_vregs = cfg->num_vregs; + +- data->active_state = pinctrl_lookup_state(dev->pins->p, "active"); +- if (IS_ERR(data->active_state)) { +- ret = PTR_ERR(data->active_state); +- dev_err(dev, "Failed to get active_state: %d\n", ret); +- return ret; +- } +- + for (i = 0; i < data->num_vregs; i++) + data->regulators[i].supply = cfg->vregs[i].name; + ret = devm_regulator_bulk_get(dev, data->num_vregs, data->regulators); +@@ -134,6 +131,14 @@ static int qca_probe(struct platform_device *pdev) + return ret; + } + ++ data->wlan_en_gpio = devm_gpiod_get_optional(&pdev->dev, "wlan-en", GPIOD_OUT_LOW); ++ if (IS_ERR(data->wlan_en_gpio)) ++ return PTR_ERR(data->wlan_en_gpio); ++ ++ data->bt_en_gpio = devm_gpiod_get_optional(&pdev->dev, "bt-en", GPIOD_OUT_LOW); ++ if (IS_ERR(data->bt_en_gpio)) ++ return PTR_ERR(data->bt_en_gpio); ++ + data->pd.name = dev_name(dev); + data->pd.power_on = qca_power_on; + data->pd.power_off = qca_power_off; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-driver/0005-mfd-qcom-qca639x-Add-support-for-WCN6855.patch b/recipes-kernel/linux/linux-yocto/qca6390-driver/0005-mfd-qcom-qca639x-Add-support-for-WCN6855.patch new file mode 100644 index 0000000..734e778 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-driver/0005-mfd-qcom-qca639x-Add-support-for-WCN6855.patch @@ -0,0 +1,111 @@ +From 87c18e7aa2071dc0c95b76360671c3b3f2dcedec Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sat, 26 Feb 2022 21:52:08 +0300 +Subject: [PATCH 5/5] mfd: qcom-qca639x: Add support for WCN6855 + +Add support for powering up WCN6855 WiFi/BT chip. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + drivers/mfd/qcom-qca639x.c | 49 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + +diff --git a/drivers/mfd/qcom-qca639x.c b/drivers/mfd/qcom-qca639x.c +index 4de860e9bbd0..16ff767a34b0 100644 +--- a/drivers/mfd/qcom-qca639x.c ++++ b/drivers/mfd/qcom-qca639x.c +@@ -44,10 +44,38 @@ static const struct qca_cfg_data qca6390_cfg_data = { + .num_vregs = ARRAY_SIZE(qca6390_vregs), + }; + ++static const struct vreg wcn6855_vregs[] = { ++ /* 2.8 V */ ++ { "vddasd" }, /* external antenna switch */ ++ ++ /* 0.95 V */ ++ { "vddaon" }, ++ { "vddcx" }, ++ { "vddmx" }, ++ ++ /* 1.9 V - 2.1 V */ ++ { "vddrfa1" }, ++ ++ /* 1.35 V */ ++ { "vddrfa2" }, ++ ++ /* 2.2 V, optional */ ++ { "vddrfa3" }, ++ ++ /* 1.8 V */ ++ { "vddio" }, ++}; ++ ++static const struct qca_cfg_data wcn6855_cfg_data = { ++ .vregs = wcn6855_vregs, ++ .num_vregs = ARRAY_SIZE(wcn6855_vregs), ++}; ++ + struct qca_data { + size_t num_vregs; + struct device *dev; + struct generic_pm_domain pd; ++ struct gpio_desc *xo_clk_gpio; + struct gpio_desc *wlan_en_gpio; + struct gpio_desc *bt_en_gpio; + struct regulator_bulk_data regulators[]; +@@ -71,11 +99,24 @@ static int qca_power_on(struct generic_pm_domain *domain) + /* Wait for 1ms before toggling enable pins. */ + msleep(1); + ++ if (data->xo_clk_gpio) { ++ gpiod_set_value(data->xo_clk_gpio, 1); ++ ++ /*XO CLK must be asserted for some time before WLAN_EN */ ++ usleep_range(100, 200); ++ } ++ + if (data->wlan_en_gpio) + gpiod_set_value(data->wlan_en_gpio, 1); + if (data->bt_en_gpio) + gpiod_set_value(data->bt_en_gpio, 1); + ++ if (data->xo_clk_gpio) { ++ /* Assert XO CLK ~(2-5)ms before off for valid latch in HW */ ++ usleep_range(2000, 5000); ++ gpiod_set_value(data->xo_clk_gpio, 0); ++ } ++ + /* Wait for all power levels to stabilize */ + msleep(6); + +@@ -126,11 +167,18 @@ static int qca_probe(struct platform_device *pdev) + return ret; + + for (i = 0; i < data->num_vregs; i++) { ++ if (!cfg->vregs[i].load_uA) ++ continue; ++ + ret = regulator_set_load(data->regulators[i].consumer, cfg->vregs[i].load_uA); + if (ret) + return ret; + } + ++ data->xo_clk_gpio = devm_gpiod_get_optional(&pdev->dev, "xo-clk", GPIOD_OUT_LOW); ++ if (IS_ERR(data->xo_clk_gpio)) ++ return PTR_ERR(data->xo_clk_gpio); ++ + data->wlan_en_gpio = devm_gpiod_get_optional(&pdev->dev, "wlan-en", GPIOD_OUT_LOW); + if (IS_ERR(data->wlan_en_gpio)) + return PTR_ERR(data->wlan_en_gpio); +@@ -169,6 +217,7 @@ static int qca_remove(struct platform_device *pdev) + + static const struct of_device_id qca_of_match[] = { + { .compatible = "qcom,qca6390", .data = &qca6390_cfg_data }, ++ { .compatible = "qcom,wcn6855", .data = &wcn6855_cfg_data }, + { }, + }; + +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-dts/0001-arm64-dts-qcom-qrb5165-rb5-add-qca639x-power-domain.patch b/recipes-kernel/linux/linux-yocto/qca6390-dts/0001-arm64-dts-qcom-qrb5165-rb5-add-qca639x-power-domain.patch new file mode 100644 index 0000000..8cff6ab --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-dts/0001-arm64-dts-qcom-qrb5165-rb5-add-qca639x-power-domain.patch @@ -0,0 +1,66 @@ +From 97722f4d4058a76bc63042d5a3f6e239d6b6d943 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sun, 20 Dec 2020 02:44:08 +0300 +Subject: [PATCH 1/3] arm64: dts: qcom: qrb5165-rb5: add qca639x power domain + +Add QCA639x power sequencing device to be used as power domain for +respective bluetooth and WiFi devices. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 31 ++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +index dd924331b0ee..b781f33d6d2f 100644 +--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts ++++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +@@ -230,6 +230,26 @@ vreg_s4a_1p8: vreg-s4a-1p8 { + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; ++ ++ qca639x: qca639x { ++ compatible = "qcom,qca6390"; ++ #power-domain-cells = <0>; ++ ++ vddaon-supply = <&vreg_s6a_0p95>; ++ vddpmu-supply = <&vreg_s2f_0p95>; ++ vddrfa1-supply = <&vreg_s2f_0p95>; ++ vddrfa2-supply = <&vreg_s8c_1p3>; ++ vddrfa3-supply = <&vreg_s5a_1p9>; ++ vddpcie1-supply = <&vreg_s8c_1p3>; ++ vddpcie2-supply = <&vreg_s5a_1p9>; ++ vddio-supply = <&vreg_s4a_1p8>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wlan_en_state>; ++ ++ wlan-en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; ++ }; ++ + }; + + &adsp { +@@ -1243,6 +1263,17 @@ sdc2_card_det_n: sd-card-det-n-state { + function = "gpio"; + bias-pull-up; + }; ++ ++ wlan_en_state: wlan-default-state { ++ wlan-en { ++ pins = "gpio20"; ++ function = "gpio"; ++ ++ drive-strength = <16>; ++ output-low; ++ bias-pull-up; ++ }; ++ }; + }; + + &uart12 { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-dts/0002-arm64-dts-qcom-Add-Bluetooth-support-on-RB5.patch b/recipes-kernel/linux/linux-yocto/qca6390-dts/0002-arm64-dts-qcom-Add-Bluetooth-support-on-RB5.patch new file mode 100644 index 0000000..9a038e4 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-dts/0002-arm64-dts-qcom-Add-Bluetooth-support-on-RB5.patch @@ -0,0 +1,66 @@ +From e3316d8e314678931c80d2a1b70ffd53f759dc6f Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Date: Wed, 2 Sep 2020 09:03:29 +0530 +Subject: [PATCH 2/3] arm64: dts: qcom: Add Bluetooth support on RB5 + +Add Bluetooth support on RB5 using the onboard QCA6391 WLAN+BT chipset. + +Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +index b781f33d6d2f..586ac20ff956 100644 +--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts ++++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +@@ -22,6 +22,7 @@ / { + + aliases { + serial0 = &uart12; ++ serial1 = &uart6; + sdhc2 = &sdhc_2; + }; + +@@ -1232,6 +1233,17 @@ &tlmm { + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; + ++ bt_en_state: bt-default-state { ++ bt-en { ++ pins = "gpio21"; ++ function = "gpio"; ++ ++ drive-strength = <16>; ++ output-low; ++ bias-pull-up; ++ }; ++ }; ++ + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio63"; + function = "gpio"; +@@ -1276,6 +1288,18 @@ wlan-en { + }; + }; + ++&uart6 { ++ status = "okay"; ++ bluetooth { ++ compatible = "qcom,qca6390-bt"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_en_state>; ++ ++ power-domains = <&qca639x>; ++ enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ + &uart12 { + status = "okay"; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qca6390-dts/0003-arm64-dtb-qcom-qrb5165-rb5-add-power-domain-to-pcie0.patch b/recipes-kernel/linux/linux-yocto/qca6390-dts/0003-arm64-dtb-qcom-qrb5165-rb5-add-power-domain-to-pcie0.patch new file mode 100644 index 0000000..0d868f8 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qca6390-dts/0003-arm64-dtb-qcom-qrb5165-rb5-add-power-domain-to-pcie0.patch @@ -0,0 +1,35 @@ +From 0e2a4a6117aeffeb6150e0a23d90c6748ab809bf Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Date: Sun, 20 Dec 2020 03:17:50 +0300 +Subject: [PATCH 3/3] arm64: dtb: qcom: qrb5165-rb5: add power domain to pcie0 + phy + +If QCA6391 chip (connected to PCIe0) is not powered at the PCIe probe +time, PCIe0 bus probe will timeout and the device will not be detected. +To ease device power up support, use qca639x as pcie0 phy power-domain. +This allows us to make sure that QCA6391 chip is powered on before PCIe0 +probe happens. + +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Inappropriate +--- + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +index 586ac20ff956..c86b020d525e 100644 +--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts ++++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +@@ -704,6 +704,9 @@ &pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; ++ ++ /* Power on QCA639x chip, otherwise PCIe bus timeouts */ ++ power-domains = <&qca639x>; + }; + + &pcie1 { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-FROMLIST-arm64-dts-qcom-qcm6490-idp-Update-protected.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-FROMLIST-arm64-dts-qcom-qcm6490-idp-Update-protected.patch new file mode 100644 index 0000000..68a75c1 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-FROMLIST-arm64-dts-qcom-qcm6490-idp-Update-protected.patch @@ -0,0 +1,64 @@ +From 033eb03a2ab2057f3f79a20be485f5c58af20816 Mon Sep 17 00:00:00 2001 +From: Taniya Das <quic_tdas@quicinc.com> +Date: Mon, 18 Mar 2024 11:05:54 +0530 +Subject: [PATCH 1/3] FROMLIST: arm64: dts: qcom: qcm6490-idp: Update protected + clocks list + +Certain clocks are not accessible on QCM6490-IDP board, +thus mark them as protected. Update the lpassaudio node to +support the new compatible. + +Signed-off-by: Taniya Das <quic_tdas@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/r/20240318053555.20405-8-quic_tdas@quicinc.com] +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 28 +++++++++++++++++++++++- + 1 file changed, 27 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 2a5631b0fa40..3baea71e0248 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: BSD-3-Clause + /* +- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + /dts-v1/; +@@ -412,6 +412,32 @@ vreg_bob_3p296: bob { + }; + }; + ++&gcc { ++ protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, ++ <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, ++ <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, ++ <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, ++ <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, ++ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, ++ <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, ++ <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, ++ <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, ++ <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, ++ <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, ++ <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, ++ <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, ++ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, ++ <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, ++ <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, ++ <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, ++ <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; ++}; ++ ++&lpass_audiocc { ++ compatible = "qcom,qcm6490-lpassaudiocc"; ++ /delete-property/ power-domains; ++}; ++ + &qupv3_id_0 { + status = "okay"; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-PENDING-arm64-dts-qcom-qcm6490-Add-UFS-nodes-for-IDP.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-PENDING-arm64-dts-qcom-qcm6490-Add-UFS-nodes-for-IDP.patch new file mode 100644 index 0000000..c53a032 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-PENDING-arm64-dts-qcom-qcm6490-Add-UFS-nodes-for-IDP.patch @@ -0,0 +1,50 @@ +From b51bcd8342aaaffa4d08fd3474b1512f9992886e Mon Sep 17 00:00:00 2001 +From: Manish Pandey <quic_mapa@quicinc.com> +Date: Tue, 17 Oct 2023 23:46:10 +0530 +Subject: [PATCH 1/2] PENDING: arm64: dts: qcom: qcm6490: Add UFS nodes for IDP + +Add UFS host controller and Phy nodes for Qualcomm +qcm6490 IDP Board. + +Change-Id: If756cf2396ad0d82e7c607738068a634c5a1919a +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 3baea71e0248..424cd9c2b092 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -463,6 +463,25 @@ &uart5 { + status = "okay"; + }; + ++&ufs_mem_hc { ++ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; ++ vcc-supply = <&vreg_l7b_2p952>; ++ vcc-max-microamp = <800000>; ++ vccq-supply = <&vreg_l9b_1p2>; ++ vccq-max-microamp = <900000>; ++ vccq2-supply = <&vreg_l9b_1p2>; ++ vccq2-max-microamp = <900000>; ++ ++ status = "okay"; ++}; ++ ++&ufs_mem_phy { ++ vdda-phy-supply = <&vreg_l10c_0p88>; ++ vdda-pll-supply = <&vreg_l6b_1p2>; ++ ++ status = "okay"; ++}; ++ + &usb_1 { + status = "okay"; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Correct-the-.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Correct-the-.patch new file mode 100644 index 0000000..194e302 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Correct-the-.patch @@ -0,0 +1,37 @@ +From a324118e3760a4a62e623bea5a9f5f262ef97436 Mon Sep 17 00:00:00 2001 +From: Atul Dhudase <quic_adhudase@quicinc.com> +Date: Tue, 2 Apr 2024 15:52:03 +0530 +Subject: [PATCH 1/2] UPSTREAM: arm64: dts: qcom: qcs6490-rb3gen2: Correct the + voltage setting for vph_pwr + +Min and max voltages for vph_pwr should be same, otherwise rpmh +will not probe, so correcting the min and max voltages for vph_pwr. + +Fixes: 04cf333afc75 ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts") +Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231220110015.25378-3-quic_kbajaj@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 5f439c0e64b877c1f9cc7f0bed894b6df45d43d] +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index 4266a1200669..d519f2064ea3 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -121,8 +121,8 @@ debug_vm_mem: debug-vm@d0600000 { + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <4350000>; ++ regulator-min-microvolt = <3700000>; ++ regulator-max-microvolt = <3700000>; + }; + }; + +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-Fairphone-.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-Fairphone-.patch new file mode 100644 index 0000000..0010b69 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0001-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-Fairphone-.patch @@ -0,0 +1,43 @@ +From 4228299b08120ce8afef3271768dcfa5e760c2c6 Mon Sep 17 00:00:00 2001 +From: Luca Weiss <luca.weiss@fairphone.com> +Date: Tue, 19 Sep 2023 14:46:00 +0200 +Subject: [PATCH 1/4] UPSTREAM: dt-bindings: arm: qcom: Add QCM6490 Fairphone 5 + +Fairphone 5 is a smartphone based on the QCM6490 SoC. + +Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-6-14bb7cedadf5@fairphone.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 4b1a16d776b474345b12f834de1fd42bca226d90] +--- + Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml +index 90f31beb80c2..adee504bffdb 100644 +--- a/Documentation/devicetree/bindings/arm/qcom.yaml ++++ b/Documentation/devicetree/bindings/arm/qcom.yaml +@@ -50,6 +50,7 @@ description: | + msm8998 + qcs404 + qcm2290 ++ qcm6490 + qdu1000 + qrb2210 + qrb4210 +@@ -391,6 +392,11 @@ properties: + - const: qcom,qrb2210 + - const: qcom,qcm2290 + ++ - items: ++ - enum: ++ - fairphone,fp5 ++ - const: qcom,qcm6490 ++ + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform + items: + - enum: +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-PENDING-arm64-dts-qcom-Add-UFS-nodes-for-qcs6490-rb3.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-PENDING-arm64-dts-qcom-Add-UFS-nodes-for-qcs6490-rb3.patch new file mode 100644 index 0000000..8ac2a74 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-PENDING-arm64-dts-qcom-Add-UFS-nodes-for-qcs6490-rb3.patch @@ -0,0 +1,49 @@ +From 4c0b2673c7d702483a526ebe279d57c4eece8f09 Mon Sep 17 00:00:00 2001 +From: Atul Dhudase <quic_adhudase@quicinc.com> +Date: Fri, 22 Mar 2024 14:06:21 +0530 +Subject: [PATCH 2/2] PENDING: arm64: dts: qcom: Add UFS nodes for + qcs6490-rb3gen2 + +Add UFS host controller and Phy nodes for Qualcomm +qcs6490-rb3gen2 board. + +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index 84137086c1f6..6dbeb182d014 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -446,6 +446,25 @@ &uart5 { + status = "okay"; + }; + ++&ufs_mem_hc { ++ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; ++ vcc-supply = <&vreg_l7b_2p952>; ++ vcc-max-microamp = <800000>; ++ vccq-supply = <&vreg_l9b_1p2>; ++ vccq-max-microamp = <900000>; ++ vccq2-supply = <&vreg_l9b_1p2>; ++ vccq2-max-microamp = <900000>; ++ ++ status = "okay"; ++}; ++ ++&ufs_mem_phy { ++ vdda-phy-supply = <&vreg_l10c_0p88>; ++ vdda-pll-supply = <&vreg_l6b_1p2>; ++ ++ status = "okay"; ++}; ++ + &usb_1 { + status = "okay"; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcm6490-idp-Correct-the-volt.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcm6490-idp-Correct-the-volt.patch new file mode 100644 index 0000000..b161099 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcm6490-idp-Correct-the-volt.patch @@ -0,0 +1,37 @@ +From a9d2e53efb1dd1bfea1be9c66ddcf319246aa140 Mon Sep 17 00:00:00 2001 +From: Atul Dhudase <quic_adhudase@quicinc.com> +Date: Tue, 2 Apr 2024 15:56:30 +0530 +Subject: [PATCH 2/2] UPSTREAM: arm64: dts: qcom: qcm6490-idp: Correct the + voltage setting for vph_pwr + +Min and max voltages for vph_pwr should be same, otherwise rpmh +will not probe, so correcting the min and max voltages for vph_pwr. + +Fixes: 9af6a9f32ad0 ("arm64: dts: qcom: Add base qcm6490 idp board dts") +Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231220110015.25378-2-quic_kbajaj@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git aa56130e88de50773f84de4039c7de81ab783744] +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 123e0e1b9e84..89e653c93ae8 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -120,8 +120,8 @@ debug_vm_mem: debug-vm@d0600000 { + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <4350000>; ++ regulator-min-microvolt = <3700000>; ++ regulator-max-microvolt = <3700000>; + }; + }; + +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Declare-GCC-.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Declare-GCC-.patch new file mode 100644 index 0000000..5834979 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Declare-GCC-.patch @@ -0,0 +1,56 @@ +From 75600814c282c7e7de67b94786d1dee0b9ddcfe2 Mon Sep 17 00:00:00 2001 +From: Atul Dhudase <quic_adhudase@quicinc.com> +Date: Tue, 2 Apr 2024 12:28:35 +0530 +Subject: [PATCH 2/3] UPSTREAM: arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC + clocks protected + +The SC7280 GCC binding describes clocks which, due to the difference in +security model, are not accessible on the RB3gen2 - in the same way seen +on QCM6490. + +Mark these clocks as protected, to allow the board to boot. In contrast +to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this +does not need to be "protected" and is used on the RB3Gen2 board. + +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> +Link: https://lore.kernel.org/r/20240209-qcm6490-gcc-protected-clocks-v2-1-11cd5fc13bd0@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7c6bef576a8891abce08d448165b53328032aa5f] +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index 0beab54c051e..b642ba9d4c00 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -410,6 +410,23 @@ vreg_bob_3p296: bob { + }; + }; + ++&gcc { ++ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, ++ <GCC_MSS_CFG_AHB_CLK>, ++ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, ++ <GCC_MSS_OFFLINE_AXI_CLK>, ++ <GCC_MSS_Q6SS_BOOT_CLK_SRC>, ++ <GCC_MSS_Q6_MEMNOC_AXI_CLK>, ++ <GCC_MSS_SNOC_AXI_CLK>, ++ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, ++ <GCC_QSPI_CORE_CLK>, ++ <GCC_QSPI_CORE_CLK_SRC>, ++ <GCC_SEC_CTRL_CLK_SRC>, ++ <GCC_WPSS_AHB_BDG_MST_CLK>, ++ <GCC_WPSS_AHB_CLK>, ++ <GCC_WPSS_RSCP_CLK>; ++}; ++ + &qupv3_id_0 { + status = "okay"; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-IDP-and-QC.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-IDP-and-QC.patch new file mode 100644 index 0000000..7951f09 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0002-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-IDP-and-QC.patch @@ -0,0 +1,39 @@ +From 4557d6178af17473f392968474b5ca0da56b1175 Mon Sep 17 00:00:00 2001 +From: Komal Bajaj <quic_kbajaj@quicinc.com> +Date: Wed, 29 Nov 2023 12:28:14 +0530 +Subject: [PATCH 2/4] UPSTREAM: dt-bindings: arm: qcom: Add QCM6490 IDP and + QCS6490 RB3Gen2 board + +Document the qcom,qcm6490-idp and qcs6490-rb3gen2 boards. +qcm6490-idp based off qcm6490 SoC derived from sc7280 meant for +various form factor including IoT and qcs6490-rb3gen2 based off +qcs6490 SoC derivative of qcm6490 without internal modem. + +Co-developed by: Naina Mehta <quic_nainmeht@quicinc.com> +Signed-off by: Naina Mehta <quic_nainmeht@quicinc.com> + +Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Link: https://lore.kernel.org/r/20231129065816.26409-2-quic_kbajaj@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 06fd1dd1efde4a0bcc874de03558f6e0ba3817eb] +--- + Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml +index adee504bffdb..e45e293457d3 100644 +--- a/Documentation/devicetree/bindings/arm/qcom.yaml ++++ b/Documentation/devicetree/bindings/arm/qcom.yaml +@@ -395,6 +395,8 @@ properties: + - items: + - enum: + - fairphone,fp5 ++ - qcom,qcm6490-idp ++ - qcom,qcs6490-rb3gen2 + - const: qcom,qcm6490 + + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-BACKPORT-FROMLIST-arm64-dts-qcom-qcs6490-rb3gen2-Upd.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-BACKPORT-FROMLIST-arm64-dts-qcom-qcs6490-rb3gen2-Upd.patch new file mode 100644 index 0000000..a1716fd --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-BACKPORT-FROMLIST-arm64-dts-qcom-qcs6490-rb3gen2-Upd.patch @@ -0,0 +1,41 @@ +From 85e1d98a2b1d8515d242154aef320a3900fb5030 Mon Sep 17 00:00:00 2001 +From: Taniya Das <quic_tdas@quicinc.com> +Date: Mon, 18 Mar 2024 11:05:55 +0530 +Subject: [PATCH 3/3] BACKPORT: FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2: + Update the LPASS audio node + +Update the lpassaudio node to support the new compatible. + +Signed-off-by: Taniya Das <quic_tdas@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/r/20240318053555.20405-9-quic_tdas@quicinc.com] +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index b642ba9d4c00..84137086c1f6 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: BSD-3-Clause + /* +- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + /dts-v1/; +@@ -427,6 +427,11 @@ &gcc { + <GCC_WPSS_RSCP_CLK>; + }; + ++&lpass_audiocc { ++ compatible = "qcom,qcm6490-lpassaudiocc"; ++ /delete-property/ power-domains; ++}; ++ + &qupv3_id_0 { + status = "okay"; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-UPSTREAM-arm64-dts-qcom-Add-base-qcm6490-id.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-UPSTREAM-arm64-dts-qcom-Add-base-qcm6490-id.patch new file mode 100644 index 0000000..bb60422 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0003-UPSTREAM-arm64-dts-qcom-Add-base-qcm6490-id.patch @@ -0,0 +1,508 @@ +From 4c6d64ebad9067be2a5138ab202f570b0e71d3f0 Mon Sep 17 00:00:00 2001 +From: Komal Bajaj <quic_kbajaj@quicinc.com> +Date: Wed, 29 Nov 2023 12:28:15 +0530 +Subject: [PATCH 3/4] UPSTREAM: arm64: dts: qcom: Add base qcm6490 + idp board dts + +Add DTS for Qualcomm IDP platform using QCM6490 SoC. +This adds debug uart, eMMC and usb support along with +regulators found on this board. + +Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> +Link: https://lore.kernel.org/r/20231129065816.26409-3-quic_kbajaj@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 9af6a9f32ad0023b1d682af213a0c8c2aa1dce29] +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 465 +++++++++++++++++++++++ + 2 files changed, 466 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/qcm6490-idp.dts + +diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile +index 2cca20563a1d..3199b1b8db13 100644 +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb ++dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb + dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +new file mode 100644 +index 000000000000..2a5631b0fa40 +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -0,0 +1,465 @@ ++// SPDX-License-Identifier: BSD-3-Clause ++/* ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include <dt-bindings/regulator/qcom,rpmh-regulator.h> ++#include "sc7280.dtsi" ++#include "pm7325.dtsi" ++#include "pm8350c.dtsi" ++#include "pmk8350.dtsi" ++ ++/delete-node/ &ipa_fw_mem; ++/delete-node/ &rmtfs_mem; ++/delete-node/ &video_mem; ++/delete-node/ &wlan_ce_mem; ++/delete-node/ &xbl_mem; ++ ++/ { ++ model = "Qualcomm Technologies, Inc. QCM6490 IDP"; ++ compatible = "qcom,qcm6490-idp", "qcom,qcm6490"; ++ chassis-type = "embedded"; ++ ++ aliases { ++ serial0 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ xbl_mem: xbl@80700000 { ++ reg = <0x0 0x80700000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { ++ reg = <0x0 0x81800000 0x0 0x1e00000>; ++ no-map; ++ }; ++ ++ camera_mem: camera@84300000 { ++ reg = <0x0 0x84300000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ wpss_mem: wpss@84800000 { ++ reg = <0x0 0x84800000 0x0 0x1900000>; ++ no-map; ++ }; ++ ++ adsp_mem: adsp@86100000 { ++ reg = <0x0 0x86100000 0x0 0x2800000>; ++ no-map; ++ }; ++ ++ cdsp_mem: cdsp@88900000 { ++ reg = <0x0 0x88900000 0x0 0x1e00000>; ++ no-map; ++ }; ++ ++ video_mem: video@8a700000 { ++ reg = <0x0 0x8a700000 0x0 0x700000>; ++ no-map; ++ }; ++ ++ cvp_mem: cvp@8ae00000 { ++ reg = <0x0 0x8ae00000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ ipa_fw_mem: ipa-fw@8b300000 { ++ reg = <0x0 0x8b300000 0x0 0x10000>; ++ no-map; ++ }; ++ ++ ipa_gsi_mem: ipa-gsi@8b310000 { ++ reg = <0x0 0x8b310000 0x0 0xa000>; ++ no-map; ++ }; ++ ++ gpu_microcode_mem: gpu-microcode@8b31a000 { ++ reg = <0x0 0x8b31a000 0x0 0x2000>; ++ no-map; ++ }; ++ ++ mpss_mem: mpss@8b800000 { ++ reg = <0x0 0x8b800000 0x0 0xf600000>; ++ no-map; ++ }; ++ ++ tz_stat_mem: tz-stat@c0000000 { ++ reg = <0x0 0xc0000000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ tags_mem: tags@c0100000 { ++ reg = <0x0 0xc0100000 0x0 0x1200000>; ++ no-map; ++ }; ++ ++ qtee_mem: qtee@c1300000 { ++ reg = <0x0 0xc1300000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ trusted_apps_mem: trusted_apps@c1800000 { ++ reg = <0x0 0xc1800000 0x0 0x1c00000>; ++ no-map; ++ }; ++ ++ debug_vm_mem: debug-vm@d0600000 { ++ reg = <0x0 0xd0600000 0x0 0x100000>; ++ no-map; ++ }; ++ }; ++ ++ vph_pwr: vph-pwr-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vph_pwr"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <4350000>; ++ }; ++}; ++ ++&apps_rsc { ++ regulators-0 { ++ compatible = "qcom,pm7325-rpmh-regulators"; ++ qcom,pmic-id = "b"; ++ ++ vdd-s1-supply = <&vph_pwr>; ++ vdd-s2-supply = <&vph_pwr>; ++ vdd-s3-supply = <&vph_pwr>; ++ vdd-s4-supply = <&vph_pwr>; ++ vdd-s5-supply = <&vph_pwr>; ++ vdd-s6-supply = <&vph_pwr>; ++ vdd-s7-supply = <&vph_pwr>; ++ vdd-s8-supply = <&vph_pwr>; ++ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; ++ vdd-l2-l7-supply = <&vreg_bob_3p296>; ++ vdd-l3-supply = <&vreg_s2b_0p876>; ++ vdd-l5-supply = <&vreg_s2b_0p876>; ++ vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; ++ vdd-l8-supply = <&vreg_s7b_0p972>; ++ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; ++ vdd-l13-supply = <&vreg_s7b_0p972>; ++ vdd-l14-l16-supply = <&vreg_s8b_1p272>; ++ ++ vreg_s1b_1p872: smps1 { ++ regulator-min-microvolt = <1840000>; ++ regulator-max-microvolt = <2040000>; ++ }; ++ ++ vreg_s2b_0p876: smps2 { ++ regulator-min-microvolt = <570070>; ++ regulator-max-microvolt = <1050000>; ++ }; ++ ++ vreg_s7b_0p972: smps7 { ++ regulator-min-microvolt = <535000>; ++ regulator-max-microvolt = <1120000>; ++ }; ++ ++ vreg_s8b_1p272: smps8 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; ++ }; ++ ++ vreg_l1b_0p912: ldo1 { ++ regulator-min-microvolt = <825000>; ++ regulator-max-microvolt = <925000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l2b_3p072: ldo2 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l3b_0p504: ldo3 { ++ regulator-min-microvolt = <312000>; ++ regulator-max-microvolt = <910000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l4b_0p752: ldo4 { ++ regulator-min-microvolt = <752000>; ++ regulator-max-microvolt = <820000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ reg_l5b_0p752: ldo5 { ++ regulator-min-microvolt = <552000>; ++ regulator-max-microvolt = <832000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l6b_1p2: ldo6 { ++ regulator-min-microvolt = <1140000>; ++ regulator-max-microvolt = <1260000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l7b_2p952: ldo7 { ++ regulator-min-microvolt = <2400000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l8b_0p904: ldo8 { ++ regulator-min-microvolt = <870000>; ++ regulator-max-microvolt = <970000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l9b_1p2: ldo9 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1304000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l11b_1p504: ldo11 { ++ regulator-min-microvolt = <1504000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l12b_0p751: ldo12 { ++ regulator-min-microvolt = <751000>; ++ regulator-max-microvolt = <824000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l13b_0p53: ldo13 { ++ regulator-min-microvolt = <530000>; ++ regulator-max-microvolt = <824000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l14b_1p08: ldo14 { ++ regulator-min-microvolt = <1080000>; ++ regulator-max-microvolt = <1304000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l15b_0p765: ldo15 { ++ regulator-min-microvolt = <765000>; ++ regulator-max-microvolt = <1020000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l16b_1p1: ldo16 { ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l17b_1p7: ldo17 { ++ regulator-min-microvolt = <1700000>; ++ regulator-max-microvolt = <1900000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l18b_1p8: ldo18 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l19b_1p8: ldo19 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM ++ RPMH_REGULATOR_MODE_HPM>; ++ }; ++ }; ++ ++ regulators-1 { ++ compatible = "qcom,pm8350c-rpmh-regulators"; ++ qcom,pmic-id = "c"; ++ ++ vdd-s1-supply = <&vph_pwr>; ++ vdd-s2-supply = <&vph_pwr>; ++ vdd-s3-supply = <&vph_pwr>; ++ vdd-s4-supply = <&vph_pwr>; ++ vdd-s5-supply = <&vph_pwr>; ++ vdd-s6-supply = <&vph_pwr>; ++ vdd-s7-supply = <&vph_pwr>; ++ vdd-s8-supply = <&vph_pwr>; ++ vdd-s9-supply = <&vph_pwr>; ++ vdd-s10-supply = <&vph_pwr>; ++ vdd-l1-l12-supply = <&vreg_s1b_1p872>; ++ vdd-l2-l8-supply = <&vreg_s1b_1p872>; ++ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; ++ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; ++ vdd-l10-supply = <&vreg_s7b_0p972>; ++ vdd-bob-supply = <&vph_pwr>; ++ ++ vreg_s1c_2p19: smps1 { ++ regulator-min-microvolt = <2190000>; ++ regulator-max-microvolt = <2210000>; ++ }; ++ ++ vreg_s2c_0p752: smps2 { ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <800000>; ++ }; ++ ++ vreg_s5c_0p752: smps5 { ++ regulator-min-microvolt = <465000>; ++ regulator-max-microvolt = <1050000>; ++ }; ++ ++ vreg_s7c_0p752: smps7 { ++ regulator-min-microvolt = <465000>; ++ regulator-max-microvolt = <800000>; ++ }; ++ ++ vreg_s9c_1p084: smps9 { ++ regulator-min-microvolt = <1010000>; ++ regulator-max-microvolt = <1170000>; ++ }; ++ ++ vreg_l1c_1p8: ldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1980000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l2c_1p62: ldo2 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <1980000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l3c_2p8: ldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <3540000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l4c_1p62: ldo4 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l5c_1p62: ldo5 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l6c_2p96: ldo6 { ++ regulator-min-microvolt = <1650000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l7c_3p0: ldo7 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l8c_1p62: ldo8 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l9c_2p96: ldo9 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <35440000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l10c_0p88: ldo10 { ++ regulator-min-microvolt = <720000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l11c_2p8: ldo11 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l12c_1p65: ldo12 { ++ regulator-min-microvolt = <1650000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l13c_2p7: ldo13 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_bob_3p296: bob { ++ regulator-min-microvolt = <3008000>; ++ regulator-max-microvolt = <3960000>; ++ }; ++ }; ++}; ++ ++&qupv3_id_0 { ++ status = "okay"; ++}; ++ ++&sdhc_1 { ++ non-removable; ++ no-sd; ++ no-sdio; ++ ++ vmmc-supply = <&vreg_l7b_2p952>; ++ vqmmc-supply = <&vreg_l19b_1p8>; ++ ++ status = "okay"; ++}; ++ ++&tlmm { ++ gpio-reserved-ranges = <32 2>, /* ADSP */ ++ <48 4>; /* NFC */ ++}; ++ ++&uart5 { ++ compatible = "qcom,geni-debug-uart"; ++ status = "okay"; ++}; ++ ++&usb_1 { ++ status = "okay"; ++}; ++ ++&usb_1_dwc3 { ++ dr_mode = "peripheral"; ++}; ++ ++&usb_1_hsphy { ++ vdda-pll-supply = <&vreg_l10c_0p88>; ++ vdda33-supply = <&vreg_l2b_3p072>; ++ vdda18-supply = <&vreg_l1c_1p8>; ++ ++ status = "okay"; ++}; ++ ++&usb_1_qmpphy { ++ vdda-phy-supply = <&vreg_l6b_1p2>; ++ vdda-pll-supply = <&vreg_l1b_0p912>; ++ ++ status = "okay"; ++}; ++ ++&wifi { ++ memory-region = <&wlan_fw_mem>; ++}; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0004-UPSTREAM-arm64-dts-qcom-Add-base-qcs6490-rb3gen2-boa.patch b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0004-UPSTREAM-arm64-dts-qcom-Add-base-qcs6490-rb3gen2-boa.patch new file mode 100644 index 0000000..ce4c246 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-board-dts/0004-UPSTREAM-arm64-dts-qcom-Add-base-qcs6490-rb3gen2-boa.patch @@ -0,0 +1,497 @@ +From 35f473c0500b63f21de7f6ea144f2b5a327a180e Mon Sep 17 00:00:00 2001 +From: Komal Bajaj <quic_kbajaj@quicinc.com> +Date: Wed, 29 Nov 2023 12:28:16 +0530 +Subject: [PATCH 4/4] UPSTREAM: arm64: dts: qcom: Add base qcs6490-rb3gen2 + board dts + +Add DTS for Qualcomm qcs6490-rb3gen2 board which uses +QCS6490 SoC. This adds debug uart and usb support along +with regulators found on this board. + +Co-developed-by: Naina Mehta <quic_nainmeht@quicinc.com> +Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com> +Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> +Link: https://lore.kernel.org/r/20231129065816.26409-4-quic_kbajaj@quicinc.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 04cf333afc757d8fd3c674c6c3f5f86c7755b4d4] +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 452 +++++++++++++++++++ + 2 files changed, 453 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts + +diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile +index 3199b1b8db13..28178644834a 100644 +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb ++dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb + dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb + dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +new file mode 100644 +index 000000000000..0beab54c051e +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -0,0 +1,452 @@ ++// SPDX-License-Identifier: BSD-3-Clause ++/* ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++/* PM7250B is configured to use SID8/9 */ ++#define PM7250B_SID 8 ++#define PM7250B_SID1 9 ++ ++#include <dt-bindings/regulator/qcom,rpmh-regulator.h> ++#include "sc7280.dtsi" ++#include "pm7250b.dtsi" ++#include "pm7325.dtsi" ++#include "pm8350c.dtsi" ++#include "pmk8350.dtsi" ++ ++/delete-node/ &ipa_fw_mem; ++/delete-node/ &remoteproc_mpss; ++/delete-node/ &rmtfs_mem; ++/delete-node/ &video_mem; ++/delete-node/ &wlan_ce_mem; ++/delete-node/ &xbl_mem; ++ ++/ { ++ model = "Qualcomm Technologies, Inc. Robotics RB3gen2"; ++ compatible = "qcom,qcs6490-rb3gen2", "qcom,qcm6490"; ++ chassis-type = "embedded"; ++ ++ aliases { ++ serial0 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ xbl_mem: xbl@80700000 { ++ reg = <0x0 0x80700000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { ++ reg = <0x0 0x81800000 0x0 0x1e00000>; ++ no-map; ++ }; ++ ++ camera_mem: camera@84300000 { ++ reg = <0x0 0x84300000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ wpss_mem: wpss@84800000 { ++ reg = <0x0 0x84800000 0x0 0x1900000>; ++ no-map; ++ }; ++ ++ adsp_mem: adsp@86100000 { ++ reg = <0x0 0x86100000 0x0 0x2800000>; ++ no-map; ++ }; ++ ++ cdsp_mem: cdsp@88900000 { ++ reg = <0x0 0x88900000 0x0 0x1e00000>; ++ no-map; ++ }; ++ ++ video_mem: video@8a700000 { ++ reg = <0x0 0x8a700000 0x0 0x700000>; ++ no-map; ++ }; ++ ++ cvp_mem: cvp@8ae00000 { ++ reg = <0x0 0x8ae00000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ ipa_fw_mem: ipa-fw@8b300000 { ++ reg = <0x0 0x8b300000 0x0 0x10000>; ++ no-map; ++ }; ++ ++ ipa_gsi_mem: ipa-gsi@8b310000 { ++ reg = <0x0 0x8b310000 0x0 0xa000>; ++ no-map; ++ }; ++ ++ gpu_microcode_mem: gpu-microcode@8b31a000 { ++ reg = <0x0 0x8b31a000 0x0 0x2000>; ++ no-map; ++ }; ++ ++ tz_stat_mem: tz-stat@c0000000 { ++ reg = <0x0 0xc0000000 0x0 0x100000>; ++ no-map; ++ }; ++ ++ tags_mem: tags@c0100000 { ++ reg = <0x0 0xc0100000 0x0 0x1200000>; ++ no-map; ++ }; ++ ++ qtee_mem: qtee@c1300000 { ++ reg = <0x0 0xc1300000 0x0 0x500000>; ++ no-map; ++ }; ++ ++ trusted_apps_mem: trusted_apps@c1800000 { ++ reg = <0x0 0xc1800000 0x0 0x1c00000>; ++ no-map; ++ }; ++ ++ debug_vm_mem: debug-vm@d0600000 { ++ reg = <0x0 0xd0600000 0x0 0x100000>; ++ no-map; ++ }; ++ }; ++ ++ vph_pwr: vph-pwr-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vph_pwr"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <4350000>; ++ }; ++}; ++ ++&apps_rsc { ++ regulators-0 { ++ compatible = "qcom,pm7325-rpmh-regulators"; ++ qcom,pmic-id = "b"; ++ ++ vdd-s1-supply = <&vph_pwr>; ++ vdd-s2-supply = <&vph_pwr>; ++ vdd-s3-supply = <&vph_pwr>; ++ vdd-s4-supply = <&vph_pwr>; ++ vdd-s5-supply = <&vph_pwr>; ++ vdd-s6-supply = <&vph_pwr>; ++ vdd-s7-supply = <&vph_pwr>; ++ vdd-s8-supply = <&vph_pwr>; ++ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; ++ vdd-l2-l7-supply = <&vreg_bob_3p296>; ++ vdd-l3-supply = <&vreg_s2b_0p876>; ++ vdd-l5-supply = <&vreg_s2b_0p876>; ++ vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; ++ vdd-l8-supply = <&vreg_s7b_0p972>; ++ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; ++ vdd-l13-supply = <&vreg_s7b_0p972>; ++ vdd-l14-l16-supply = <&vreg_s8b_1p272>; ++ ++ vreg_s1b_1p872: smps1 { ++ regulator-min-microvolt = <1840000>; ++ regulator-max-microvolt = <2040000>; ++ }; ++ ++ vreg_s2b_0p876: smps2 { ++ regulator-min-microvolt = <570070>; ++ regulator-max-microvolt = <1050000>; ++ }; ++ ++ vreg_s7b_0p972: smps7 { ++ regulator-min-microvolt = <535000>; ++ regulator-max-microvolt = <1120000>; ++ }; ++ ++ vreg_s8b_1p272: smps8 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; ++ }; ++ ++ vreg_l1b_0p912: ldo1 { ++ regulator-min-microvolt = <825000>; ++ regulator-max-microvolt = <925000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l2b_3p072: ldo2 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l3b_0p504: ldo3 { ++ regulator-min-microvolt = <312000>; ++ regulator-max-microvolt = <910000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l4b_0p752: ldo4 { ++ regulator-min-microvolt = <752000>; ++ regulator-max-microvolt = <820000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ reg_l5b_0p752: ldo5 { ++ regulator-min-microvolt = <552000>; ++ regulator-max-microvolt = <832000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l6b_1p2: ldo6 { ++ regulator-min-microvolt = <1140000>; ++ regulator-max-microvolt = <1260000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l7b_2p952: ldo7 { ++ regulator-min-microvolt = <2400000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l8b_0p904: ldo8 { ++ regulator-min-microvolt = <870000>; ++ regulator-max-microvolt = <970000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l9b_1p2: ldo9 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1304000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l11b_1p504: ldo11 { ++ regulator-min-microvolt = <1504000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l12b_0p751: ldo12 { ++ regulator-min-microvolt = <751000>; ++ regulator-max-microvolt = <824000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l13b_0p53: ldo13 { ++ regulator-min-microvolt = <530000>; ++ regulator-max-microvolt = <824000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l14b_1p08: ldo14 { ++ regulator-min-microvolt = <1080000>; ++ regulator-max-microvolt = <1304000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l15b_0p765: ldo15 { ++ regulator-min-microvolt = <765000>; ++ regulator-max-microvolt = <1020000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l16b_1p1: ldo16 { ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l17b_1p7: ldo17 { ++ regulator-min-microvolt = <1700000>; ++ regulator-max-microvolt = <1900000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l18b_1p8: ldo18 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l19b_1p8: ldo19 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ }; ++ ++ regulators-1 { ++ compatible = "qcom,pm8350c-rpmh-regulators"; ++ qcom,pmic-id = "c"; ++ ++ vdd-s1-supply = <&vph_pwr>; ++ vdd-s2-supply = <&vph_pwr>; ++ vdd-s3-supply = <&vph_pwr>; ++ vdd-s4-supply = <&vph_pwr>; ++ vdd-s5-supply = <&vph_pwr>; ++ vdd-s6-supply = <&vph_pwr>; ++ vdd-s7-supply = <&vph_pwr>; ++ vdd-s8-supply = <&vph_pwr>; ++ vdd-s9-supply = <&vph_pwr>; ++ vdd-s10-supply = <&vph_pwr>; ++ vdd-l1-l12-supply = <&vreg_s1b_1p872>; ++ vdd-l2-l8-supply = <&vreg_s1b_1p872>; ++ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; ++ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; ++ vdd-l10-supply = <&vreg_s7b_0p972>; ++ vdd-bob-supply = <&vph_pwr>; ++ ++ vreg_s1c_2p19: smps1 { ++ regulator-min-microvolt = <2190000>; ++ regulator-max-microvolt = <2210000>; ++ }; ++ ++ vreg_s2c_0p752: smps2 { ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <800000>; ++ }; ++ ++ vreg_s5c_0p752: smps5 { ++ regulator-min-microvolt = <465000>; ++ regulator-max-microvolt = <1050000>; ++ }; ++ ++ vreg_s7c_0p752: smps7 { ++ regulator-min-microvolt = <465000>; ++ regulator-max-microvolt = <800000>; ++ }; ++ ++ vreg_s9c_1p084: smps9 { ++ regulator-min-microvolt = <1010000>; ++ regulator-max-microvolt = <1170000>; ++ }; ++ ++ vreg_l1c_1p8: ldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1980000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l2c_1p62: ldo2 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <1980000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l3c_2p8: ldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <3540000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l4c_1p62: ldo4 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l5c_1p62: ldo5 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l6c_2p96: ldo6 { ++ regulator-min-microvolt = <1650000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l7c_3p0: ldo7 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l8c_1p62: ldo8 { ++ regulator-min-microvolt = <1620000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l9c_2p96: ldo9 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <35440000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l10c_0p88: ldo10 { ++ regulator-min-microvolt = <720000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l11c_2p8: ldo11 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l12c_1p65: ldo12 { ++ regulator-min-microvolt = <1650000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l13c_2p7: ldo13 { ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3544000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_bob_3p296: bob { ++ regulator-min-microvolt = <3008000>; ++ regulator-max-microvolt = <3960000>; ++ }; ++ }; ++}; ++ ++&qupv3_id_0 { ++ status = "okay"; ++}; ++ ++&tlmm { ++ gpio-reserved-ranges = <32 2>, /* ADSP */ ++ <48 4>; /* NFC */ ++}; ++ ++&uart5 { ++ compatible = "qcom,geni-debug-uart"; ++ status = "okay"; ++}; ++ ++&usb_1 { ++ status = "okay"; ++}; ++ ++&usb_1_dwc3 { ++ dr_mode = "peripheral"; ++}; ++ ++&usb_1_hsphy { ++ vdda-pll-supply = <&vreg_l10c_0p88>; ++ vdda33-supply = <&vreg_l2b_3p072>; ++ vdda18-supply = <&vreg_l1c_1p8>; ++ ++ status = "okay"; ++}; ++ ++&usb_1_qmpphy { ++ vdda-phy-supply = <&vreg_l6b_1p2>; ++ vdda-pll-supply = <&vreg_l1b_0p912>; ++ ++ status = "okay"; ++}; ++ ++&wifi { ++ memory-region = <&wlan_fw_mem>; ++}; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-drivers/0001-FROMGIT-phy-qcom-qmp-ufs-Add-Phy-Configuration-suppo.patch b/recipes-kernel/linux/linux-yocto/qcm6490-drivers/0001-FROMGIT-phy-qcom-qmp-ufs-Add-Phy-Configuration-suppo.patch new file mode 100644 index 0000000..cf2871c --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-drivers/0001-FROMGIT-phy-qcom-qmp-ufs-Add-Phy-Configuration-suppo.patch @@ -0,0 +1,188 @@ +From 801864e94d84f552d78e934bfe706183d7cc6901 Mon Sep 17 00:00:00 2001 +From: Nitin Rawat <quic_nitirawa@quicinc.com> +Date: Tue, 19 Sep 2023 02:20:37 +0530 +Subject: [PATCH] FROMGIT: phy: qcom-qmp-ufs: Add Phy Configuration support for + SC7280 + +Add SC7280 specific register layout and table configs. + +Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 8abe9792d1ff7e60f911b56e8a2537be7e903576] +--- + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++ + 1 file changed, 142 insertions(+) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +index 8c877b668bb9..0aca2abd77d3 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +@@ -178,6 +178,111 @@ static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), + }; + ++static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), ++}; ++ + static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), +@@ -887,6 +992,40 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { + .regs = ufsphy_v5_regs_layout, + }; + ++static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { ++ .lanes = 2, ++ ++ .offsets = &qmp_ufs_offsets, ++ ++ .tbls = { ++ .serdes = sm8150_ufsphy_serdes, ++ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), ++ .tx = sc7280_ufsphy_tx, ++ .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), ++ .rx = sc7280_ufsphy_rx, ++ .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), ++ .pcs = sc7280_ufsphy_pcs, ++ .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), ++ }, ++ .tbls_hs_b = { ++ .serdes = sm8150_ufsphy_hs_b_serdes, ++ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), ++ }, ++ .tbls_hs_g4 = { ++ .tx = sm8250_ufsphy_hs_g4_tx, ++ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), ++ .rx = sc7280_ufsphy_hs_g4_rx, ++ .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), ++ .pcs = sm8150_ufsphy_hs_g4_pcs, ++ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), ++ }, ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = ufsphy_v4_regs_layout, ++}; ++ + static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { + .lanes = 2, + +@@ -1637,6 +1776,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { + }, { + .compatible = "qcom,sa8775p-qmp-ufs-phy", + .data = &sa8775p_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc7280-qmp-ufs-phy", ++ .data = &sc7280_ufsphy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-ufs-phy", + .data = &sm8150_ufsphy_cfg, +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch new file mode 100644 index 0000000..3b17ae4 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch @@ -0,0 +1,97 @@ +From 92c06bd8d2125f45ff52c9a6819c6cd8bf7a575d Mon Sep 17 00:00:00 2001 +From: Nitin Rawat <quic_nitirawa@quicinc.com> +Date: Fri, 29 Sep 2023 18:49:34 +0530 +Subject: [PATCH] FROMLIST: arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 + soc + +Add UFS host controller and PHY nodes for sc7280 soc. + +Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/all/20230929131936.29421-3-quic_nitirawa@quicinc.com/] +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 66 ++++++++++++++++++++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 042908048d09..19705df517dd 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3321,6 +3321,72 @@ opp-202000000 { + }; + }; + ++ ufs_mem_hc: ufs@1d84000 { ++ compatible = "qcom,sc7280-ufshc", "qcom,ufshc", ++ "jedec,ufs-2.0"; ++ reg = <0x0 0x01d84000 0x0 0x3000>; ++ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&ufs_mem_phy>; ++ phy-names = "ufsphy"; ++ lanes-per-direction = <2>; ++ #reset-cells = <1>; ++ resets = <&gcc GCC_UFS_PHY_BCR>; ++ reset-names = "rst"; ++ ++ power-domains = <&gcc GCC_UFS_PHY_GDSC>; ++ required-opps = <&rpmhpd_opp_nom>; ++ ++ iommus = <&apps_smmu 0x80 0x0>; ++ dma-coherent; ++ ++ interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, ++ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_UFS_MEM_CFG 0>; ++ ++ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_UFS_PHY_AHB_CLK>, ++ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, ++ <&rpmhcc RPMH_CXO_CLK>, ++ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, ++ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, ++ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; ++ clock-names = "core_clk", ++ "bus_aggr_clk", ++ "iface_clk", ++ "core_clk_unipro", ++ "ref_clk", ++ "tx_lane0_sync_clk", ++ "rx_lane0_sync_clk", ++ "rx_lane1_sync_clk"; ++ freq-table-hz = ++ <75000000 300000000>, ++ <0 0>, ++ <0 0>, ++ <75000000 300000000>, ++ <0 0>, ++ <0 0>, ++ <0 0>, ++ <0 0>; ++ status = "disabled"; ++ }; ++ ++ ufs_mem_phy: phy@1d87000 { ++ compatible = "qcom,sc7280-qmp-ufs-phy"; ++ reg = <0x0 0x01d87000 0x0 0xe00>; ++ clocks = <&rpmhcc RPMH_CXO_CLK>, ++ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, ++ <&gcc GCC_UFS_1_CLKREF_EN>; ++ clock-names = "ref", "ref_aux", "qref"; ++ ++ resets = <&ufs_mem_hc 0>; ++ reset-names = "ufsphy"; ++ ++ #clock-cells = <1>; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-PENDING-arm64-dts-qcom-sc7280-Add-interconnect-paths.patch b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-PENDING-arm64-dts-qcom-sc7280-Add-interconnect-paths.patch new file mode 100644 index 0000000..ef6ef52 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-PENDING-arm64-dts-qcom-sc7280-Add-interconnect-paths.patch @@ -0,0 +1,31 @@ +From 0fd82fdf7e1a5d6bb1924129849ed351806e1a3d Mon Sep 17 00:00:00 2001 +From: Manish Pandey <quic_mapa@quicinc.com> +Date: Fri, 3 Nov 2023 10:11:01 +0530 +Subject: [PATCH] PENDING: arm64: dts: qcom: sc7280: Add interconnect paths to + UFSHC + +QCOM UFS host controller requires interconnect path configuration +for proper working. So add them for SC7280 SoC. + +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 19705df517dd..1217de1d3266 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3341,6 +3341,7 @@ ufs_mem_hc: ufs@1d84000 { + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_UFS_MEM_CFG 0>; ++ interconnect-names = "ufs-ddr", "cpu-ufs"; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-Use-QCOM_SCM_VMID-defines-fo.patch b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-Use-QCOM_SCM_VMID-defines-fo.patch new file mode 100644 index 0000000..27c60be --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-Use-QCOM_SCM_VMID-defines-fo.patch @@ -0,0 +1,383 @@ +From d325de87af27d2f369fa04fa0a2367600280f322 Mon Sep 17 00:00:00 2001 +From: Luca Weiss <luca.weiss@fairphone.com> +Date: Fri, 18 Aug 2023 10:06:09 +0200 +Subject: [PATCH] UPSTREAM: arm64: dts: qcom: Use QCOM_SCM_VMID defines for + qcom,vmid + +Since we have those defines available in a header, let's use them +everywhere where qcom,vmid property is used. + +Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> +Link: https://lore.kernel.org/r/20230818-qcom-vmid-defines-v1-1-45b610c96b13@fairphone.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 018c949b32df9f17f52bf0e70f976719811db233] +--- + arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +- + arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/msm8998.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 3 ++- + arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 3 ++- + arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 2 +- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 3 ++- + arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- + 19 files changed, 31 insertions(+), 19 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +index 06f8ff624181..8fda25167181 100644 +--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +@@ -115,7 +115,7 @@ rmtfs@f6c00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + /delete-node/ mba@91500000; +diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi +index 4d87cba47c76..fa8ec92ce490 100644 +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi +@@ -9,6 +9,7 @@ + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interconnect/qcom,msm8996.h> + #include <dt-bindings/interconnect/qcom,msm8996-cbf.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/soc/qcom,apr.h> +@@ -551,7 +552,7 @@ rmtfs_mem: rmtfs { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + mpss_mem: mpss@88800000 { +diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi +index f91c58c844af..c9ee2d995087 100644 +--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi +@@ -6,6 +6,7 @@ + #include <dt-bindings/clock/qcom,gpucc-msm8998.h> + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/gpio/gpio.h> + +@@ -56,7 +57,7 @@ rmtfs_mem: memory@88f00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + spss_mem: memory@8ab00000 { +diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi +index 810e529e5f2e..65b077179acc 100644 +--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi +@@ -11,6 +11,7 @@ + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,videocc-sc7180.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,osm-l3.h> + #include <dt-bindings/interconnect/qcom,sc7180.h> +@@ -687,7 +688,7 @@ rmtfs_mem: memory@94600000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 9531167c498e..cbd0f4176daa 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -13,6 +13,7 @@ + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,videocc-sc7280.h> + #include <dt-bindings/dma/qcom-gpi.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,osm-l3.h> +@@ -157,7 +158,7 @@ rmtfs_mem: memory@9c900000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +index abc66613ccaa..3ea07d094b60 100644 +--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts ++++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +@@ -6,6 +6,7 @@ + + /dts-v1/; + ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/input/gpio-keys.h> + #include <dt-bindings/input/input.h> +@@ -130,7 +131,7 @@ rmtfs_mem: rmtfs-region@85500000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + wlan_mem: wlan-region@8bc00000 { +diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +index ae008c3b0aed..a40ef23a2a4f 100644 +--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts ++++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +@@ -6,6 +6,7 @@ + + /dts-v1/; + ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/input/gpio-keys.h> + #include <dt-bindings/input/input.h> +@@ -135,7 +136,7 @@ rmtfs_mem: rmtfs-region@85500000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + wlan_mem: wlan-region@8bc00000 { +diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi +index ec6003212c4d..c17719086085 100644 +--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi +@@ -8,6 +8,7 @@ + #include <dt-bindings/clock/qcom,gpucc-sdm660.h> + #include <dt-bindings/clock/qcom,mmcc-sdm660.h> + #include <dt-bindings/clock/qcom,rpmcc.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/interconnect/qcom,sdm660.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/gpio/gpio.h> +@@ -453,7 +454,7 @@ rmtfs_mem: memory@85e00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + smem_region: smem-mem@86000000 { +diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +index f942c5afea9b..99dafc6716e7 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +@@ -111,7 +111,7 @@ rmtfs_mem: memory@f0801000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + /* rmtfs upper guard */ +diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +index 122c7128dea9..b523b5fff702 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +@@ -90,7 +90,7 @@ rmtfs_mem: rmtfs-mem@f5b01000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 { + no-map; +diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +index 9d6faeb65624..93b1582e807d 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +@@ -111,7 +111,7 @@ rmtfs_mem: memory@f6301000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +index 6db12abaa88d..e386b504e978 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts ++++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +@@ -108,7 +108,7 @@ rmtfs_mem: memory@f6301000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi +index 234d7875cd8e..6d4f86d92fec 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -813,7 +813,7 @@ rmtfs_mem: rmtfs@88f00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + qseecom_mem: qseecom@8ab00000 { +diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +index 18171c5d8a38..136e273d09a7 100644 +--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts ++++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +@@ -8,6 +8,7 @@ + /* PMK8350 (in reality a PMK8003) is configured to use SID6 instead of 0 */ + #define PMK8350_SID 6 + ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> + #include <dt-bindings/input/input.h> +@@ -75,7 +76,7 @@ memory@efe01000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi +index 26b6d84548a5..7e78bf2c6a6c 100644 +--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi +@@ -5,6 +5,7 @@ + */ + + #include <dt-bindings/dma/qcom-gpi.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/soc/qcom,rpmh-rsc.h> +@@ -720,7 +721,7 @@ rmtfs_mem: memory@89b00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + camera_mem: memory@8b700000 { +diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi +index 5ed464c37422..a72f3c470089 100644 +--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi +@@ -10,6 +10,7 @@ + #include <dt-bindings/clock/qcom,gpucc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/dma/qcom-gpi.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> +@@ -503,7 +504,7 @@ rmtfs_mem: memory@9b800000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + hyp_reserved_mem: memory@d0000000 { +diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +index 001fb2723fbb..8b29fcf483a3 100644 +--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +@@ -80,7 +80,7 @@ rmtfs_mem: memory@f3300000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + ramoops@ffc00000 { +diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi +index 91d856e5b06b..35067d441a28 100644 +--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi +@@ -10,6 +10,7 @@ + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,sm8450-videocc.h> + #include <dt-bindings/dma/qcom-gpi.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/phy/phy-qcom-qmp.h> +@@ -540,7 +541,7 @@ rmtfs_mem: memory@9fd00000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + xbl_sc_mem2: memory@a6e00000 { +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index 076715ef09d5..c0d781b30a90 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -10,6 +10,7 @@ + #include <dt-bindings/clock/qcom,sm8550-tcsr.h> + #include <dt-bindings/clock/qcom,sm8550-dispcc.h> + #include <dt-bindings/dma/qcom-gpi.h> ++#include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> +@@ -580,7 +581,7 @@ rmtfs_mem: rmtfs-region@d4a80000 { + no-map; + + qcom,client-id = <1>; +- qcom,vmid = <15>; ++ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + mpss_dsm_mem: mpss-dsm-region@d4d00000 { +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-sc7280-Move-video-firmware-t.patch b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-sc7280-Move-video-firmware-t.patch new file mode 100644 index 0000000..966d4d1 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-sc7280-Move-video-firmware-t.patch @@ -0,0 +1,82 @@ +From 65d0e0ecf6725459457162b33d02333888bfa25e Mon Sep 17 00:00:00 2001 +From: Luca Weiss <luca.weiss@fairphone.com> +Date: Fri, 1 Dec 2023 10:33:19 +0100 +Subject: [PATCH] UPSTREAM: arm64: dts: qcom: sc7280: Move video-firmware to + chrome-common + +If the video-firmware node is present, the venus driver assumes we're on +a system that doesn't use TZ for starting venus, like on ChromeOS +devices. + +Move the video-firmware node to chrome-common.dtsi so we can use venus +on a non-ChromeOS devices. We also need to move the secure SID 0x2184 +for iommu since (on some boards) we cannot touch that. + +At the same time also disable the venus node by default in the dtsi, +like it's done on other SoCs. + +Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> +Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> +Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com> +Link: https://lore.kernel.org/r/20231201-sc7280-venus-pas-v3-2-bc132dc5fc30@fairphone.com +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 82066cdb17608abc95192632fd5c702be8e57ab5] +--- + arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 11 +++++++++++ + arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++------ + 2 files changed, 14 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +index 5d462ae14ba1..459ff877df54 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +@@ -104,6 +104,17 @@ &scm { + dma-coherent; + }; + ++&venus { ++ iommus = <&apps_smmu 0x2180 0x20>, ++ <&apps_smmu 0x2184 0x20>; ++ ++ status = "okay"; ++ ++ video-firmware { ++ iommus = <&apps_smmu 0x21a2 0x0>; ++ }; ++}; ++ + &watchdog { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index cbd0f4176daa..1c136ad878ed 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3725,10 +3725,11 @@ venus: video-codec@aa00000 { + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cpu-cfg", "video-mem"; + +- iommus = <&apps_smmu 0x2180 0x20>, +- <&apps_smmu 0x2184 0x20>; ++ iommus = <&apps_smmu 0x2180 0x20>; + memory-region = <&video_mem>; + ++ status = "disabled"; ++ + video-decoder { + compatible = "venus-decoder"; + }; +@@ -3737,10 +3738,6 @@ video-encoder { + compatible = "venus-encoder"; + }; + +- video-firmware { +- iommus = <&apps_smmu 0x21a2 0x0>; +- }; +- + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/qcom.scc b/recipes-kernel/linux/linux-yocto/qcom.scc new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcom.scc diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0001_dt_bindings_display_msm_qcm2290_mdss_use_the_non_deprecated_dsi_compat.patch b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0001_dt_bindings_display_msm_qcm2290_mdss_use_the_non_deprecated_dsi_compat.patch new file mode 100644 index 0000000..04ccd0f --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0001_dt_bindings_display_msm_qcm2290_mdss_use_the_non_deprecated_dsi_compat.patch @@ -0,0 +1,45 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: dt-bindings: display: msm: qcm2290-mdss: Use the non-deprecated DSI compat +Date: Wed, 29 Nov 2023 15:43:58 +0100 + +The "qcom,dsi-ctrl-6g-qcm2290" has been deprecated in commit 0c0f65c6dd44 +("dt-bindings: msm: dsi-controller-main: Add compatible strings for every +current SoC"), but the example hasn't been updated to reflect that. + +Fix that. + +Fixes: 0c0f65c6dd44 ("dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC") +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://gitlab.freedesktop.org/lumag/msm/-/commit/25daacc60394] +--- + .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +index 5ad155612b6c..d71a8e09a798 100644 +--- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml ++++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +@@ -56,7 +56,9 @@ patternProperties: + + properties: + compatible: +- const: qcom,dsi-ctrl-6g-qcm2290 ++ items: ++ - const: qcom,qcm2290-dsi-ctrl ++ - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object +@@ -136,7 +138,8 @@ examples: + }; + + dsi@5e94000 { +- compatible = "qcom,dsi-ctrl-6g-qcm2290"; ++ compatible = "qcom,qcm2290-dsi-ctrl", ++ "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0003_dt_bindings_interconnect_qcom_msm8998_bwmon_add_qcm2290_bwmon_instance.patch b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0003_dt_bindings_interconnect_qcom_msm8998_bwmon_add_qcm2290_bwmon_instance.patch new file mode 100644 index 0000000..2d2488d --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0003_dt_bindings_interconnect_qcom_msm8998_bwmon_add_qcm2290_bwmon_instance.patch @@ -0,0 +1,27 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: dt-bindings: interconnect: qcom,msm8998-bwmon: Add QCM2290 bwmon instance +Date: Wed, 29 Nov 2023 15:44:00 +0100 + +QCM2290 has a single BWMONv4 intance for CPU. Document it. + +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Submitted [https://lore.kernel.org/linux-arm-msm/20231125-topic-rb1_feat-v3-3-4cbb567743bb@linaro.org/] +--- + Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +index 7cb8df757477..a88cea732370 100644 +--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml ++++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +@@ -25,6 +25,7 @@ properties: + - const: qcom,msm8998-bwmon # BWMON v4 + - items: + - enum: ++ - qcom,qcm2290-cpu-bwmon + - qcom,sc7180-cpu-bwmon + - qcom,sc7280-cpu-bwmon + - qcom,sc8280xp-cpu-bwmon +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0004_dt_bindings_firmware_qcom_scm_allow_interconnect_for_everyone.patch b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0004_dt_bindings_firmware_qcom_scm_allow_interconnect_for_everyone.patch new file mode 100644 index 0000000..96a0624 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0004_dt_bindings_firmware_qcom_scm_allow_interconnect_for_everyone.patch @@ -0,0 +1,42 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: dt-bindings: firmware: qcom,scm: Allow interconnect for everyone +Date: Wed, 29 Nov 2023 15:44:01 +0100 + +Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane. +Allow this property to be present, no matter the SoC. + +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 56fdc35ef067c8dffee22038dd3a84bb3fa6d2a4] +--- + Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 15 --------------- + 1 file changed, 15 deletions(-) + +diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +index 0613a37a851a..f3a87a8426d0 100644 +--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml ++++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +@@ -178,21 +178,6 @@ allOf: + minItems: 3 + maxItems: 3 + +- # Interconnects +- - if: +- not: +- properties: +- compatible: +- contains: +- enum: +- - qcom,scm-qdu1000 +- - qcom,scm-sc8280xp +- - qcom,scm-sm8450 +- - qcom,scm-sm8550 +- then: +- properties: +- interconnects: false +- + # Interrupts + - if: + not: +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0005_iommu_arm_smmu_qcom_add_qcm2290_mdss_compatible.patch b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0005_iommu_arm_smmu_qcom_add_qcm2290_mdss_compatible.patch new file mode 100644 index 0000000..82a4091 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-drivers/0005_iommu_arm_smmu_qcom_add_qcm2290_mdss_compatible.patch @@ -0,0 +1,28 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: iommu/arm-smmu-qcom: Add QCM2290 MDSS compatible +Date: Wed, 29 Nov 2023 15:44:02 +0100 + +Add the QCM2290 MDSS compatible to clients compatible list, as it also +needs the workarounds. + +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/will/c/28af105cb650] +--- + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +index 549ae4dba3a6..aea5e85b20ff 100644 +--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c ++++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +@@ -245,6 +245,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { + { .compatible = "qcom,adreno" }, + { .compatible = "qcom,mdp4" }, + { .compatible = "qcom,mdss" }, ++ { .compatible = "qcom,qcm2290-mdss" }, + { .compatible = "qcom,sc7180-mdss" }, + { .compatible = "qcom,sc7180-mss-pil" }, + { .compatible = "qcom,sc7280-mdss" }, +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/0001-arm64-dts-qcom-qcm2290-Hook-up-MPM.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/0001-arm64-dts-qcom-qcm2290-Hook-up-MPM.patch new file mode 100644 index 0000000..d1e935d --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/0001-arm64-dts-qcom-qcm2290-Hook-up-MPM.patch @@ -0,0 +1,114 @@ +From e3f6a699404154e7e103f8055f21c3556721603f Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Fri, 15 Dec 2023 01:01:10 +0100 +Subject: [PATCH] arm64: dts: qcom: qcm2290: Hook up MPM + +Wire up MPM and the interrupts it provides. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231215-topic-mpm_dt-v1-3-c6636fc75ce3@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git e3f6a699404154e7e103f8055f21c3556721603f] +--- + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 ++++++++++++++++++++++----- + 1 file changed, 35 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +index ce04d0acdede..0911fb08ed63 100644 +--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi ++++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +@@ -199,6 +199,7 @@ CPU_PD3: power-domain-cpu3 { + + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; ++ power-domains = <&mpm>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; + }; +@@ -266,6 +267,24 @@ rpmpd_opp_turbo_plus: opp8 { + }; + }; + }; ++ ++ mpm: interrupt-controller { ++ compatible = "qcom,mpm"; ++ qcom,rpm-msg-ram = <&apss_mpm>; ++ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; ++ mboxes = <&apcs_glb 1>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ #power-domain-cells = <0>; ++ interrupt-parent = <&intc>; ++ qcom,mpm-pin-count = <96>; ++ qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ ++ <5 296>, /* Soundwire master_irq */ ++ <12 422>, /* DWC3 ss_phy_irq */ ++ <24 79>, /* Soundwire wake_irq */ ++ <86 183>, /* MPM wake, SPMI */ ++ <90 260>; /* QUSB2_PHY DP+DM */ ++ }; + }; + + reserved_memory: reserved-memory { +@@ -429,6 +448,7 @@ tlmm: pinctrl@500000 { + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 127>; ++ wakeup-parent = <&mpm>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +@@ -778,7 +798,7 @@ spmi_bus: spmi@1c40000 { + "obsrvr", + "intr", + "cnfg"; +- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; +@@ -793,8 +813,8 @@ tsens0: thermal-sensor@4411000 { + reg = <0x0 0x04411000 0x0 0x1ff>, + <0x0 0x04410000 0x0 0x8>; + #qcom,sensors = <10>; +- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, +- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; +@@ -813,8 +833,15 @@ bimc: interconnect@4480000 { + }; + + rpm_msg_ram: sram@45f0000 { +- compatible = "qcom,rpm-msg-ram"; ++ compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0x0 0x045f0000 0x0 0x7000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x0 0x045f0000 0x7000>; ++ ++ apss_mpm: sram@1b8 { ++ reg = <0x1b8 0x48>; ++ }; + }; + + sram@4690000 { +@@ -1293,9 +1320,10 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + usb: usb@4ef8800 { + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; + reg = <0x0 0x04ef8800 0x0 0x400>; +- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, +- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "hs_phy_irq", "ss_phy_irq"; ++ interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, ++ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "hs_phy_irq", ++ "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0006_arm64_dts_qcom_sc7180_add_the_missing_mdss_icc_path.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0006_arm64_dts_qcom_sc7180_add_the_missing_mdss_icc_path.patch new file mode 100644 index 0000000..d6d6807 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0006_arm64_dts_qcom_sc7180_add_the_missing_mdss_icc_path.patch @@ -0,0 +1,37 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: sc7180: Add the missing MDSS icc path +Date: Wed, 29 Nov 2023 15:44:03 +0100 + +MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one. +Failing to provide it may result in register accesses failing and that's +never good. + +Add the missing path. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 8786398f8686d1a4267ab52f830b25f17e6d62fc] +--- + arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi +index 11f353d416b4..9664e42faeb1 100644 +--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi +@@ -3100,8 +3100,12 @@ mdss: display-subsystem@ae00000 { + interrupt-controller; + #interrupt-cells = <1>; + +- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "mdp0-mem"; ++ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS ++ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, ++ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS ++ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + iommus = <&apps_smmu 0x800 0x2>; + +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0007_arm64_dts_qcom_sc7280_add_the_missing_mdss_icc_path.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0007_arm64_dts_qcom_sc7280_add_the_missing_mdss_icc_path.patch new file mode 100644 index 0000000..cc2fa10 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0007_arm64_dts_qcom_sc7280_add_the_missing_mdss_icc_path.patch @@ -0,0 +1,45 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: sc7280: Add the missing MDSS icc path +Date: Wed, 29 Nov 2023 15:44:04 +0100 + +MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one. +Failing to provide it may result in register accesses failing and that's +never good. + +Add the missing path. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git c657056d99878c8a8ea84d5d4a9101bcb90b47f2] +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 04bf85b0399a..41d327b1f1b6 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -15,6 +15,7 @@ + #include <dt-bindings/dma/qcom-gpi.h> + #include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,osm-l3.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> +@@ -3958,8 +3959,12 @@ mdss: display-subsystem@ae00000 { + interrupt-controller; + #interrupt-cells = <1>; + +- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; +- interconnect-names = "mdp0-mem"; ++ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS ++ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, ++ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS ++ &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + iommus = <&apps_smmu 0x900 0x402>; + +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0008_arm64_dts_qcom_qcm2290_add_display_nodes.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0008_arm64_dts_qcom_qcm2290_add_display_nodes.patch new file mode 100644 index 0000000..577adb0 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0008_arm64_dts_qcom_qcm2290_add_display_nodes.patch @@ -0,0 +1,247 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qcm2290: Add display nodes +Date: Wed, 29 Nov 2023 15:44:05 +0100 + +Add the required nodes to support display on QCM2290. + +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git a2b32096709dbf4af02675d98356a9d3ad86ff05] +--- + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 214 ++++++++++++++++++++++++++++++++++ + 1 file changed, 214 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +index d46e591e72b5..a3edc4667cc5 100644 +--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi ++++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +@@ -5,6 +5,7 @@ + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. + */ + ++#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/dma/qcom-gpi.h> +@@ -1105,6 +1106,219 @@ usb_dwc3: usb@4e00000 { + }; + }; + ++ mdss: display-subsystem@5e00000 { ++ compatible = "qcom,qcm2290-mdss"; ++ reg = <0x0 0x05e00000 0x0 0x1000>; ++ reg-names = "mdss"; ++ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ clocks = <&gcc GCC_DISP_AHB_CLK>, ++ <&gcc GCC_DISP_HF_AXI_CLK>, ++ <&dispcc DISP_CC_MDSS_MDP_CLK>; ++ clock-names = "iface", ++ "bus", ++ "core"; ++ ++ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; ++ ++ power-domains = <&dispcc MDSS_GDSC>; ++ ++ iommus = <&apps_smmu 0x420 0x2>, ++ <&apps_smmu 0x421 0x0>; ++ ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ status = "disabled"; ++ ++ mdp: display-controller@5e01000 { ++ compatible = "qcom,qcm2290-dpu"; ++ reg = <0x0 0x05e01000 0x0 0x8f000>, ++ <0x0 0x05eb0000 0x0 0x2008>; ++ reg-names = "mdp", ++ "vbif"; ++ ++ interrupt-parent = <&mdss>; ++ interrupts = <0>; ++ ++ clocks = <&gcc GCC_DISP_HF_AXI_CLK>, ++ <&dispcc DISP_CC_MDSS_AHB_CLK>, ++ <&dispcc DISP_CC_MDSS_MDP_CLK>, ++ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, ++ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; ++ clock-names = "bus", ++ "iface", ++ "core", ++ "lut", ++ "vsync"; ++ ++ operating-points-v2 = <&mdp_opp_table>; ++ power-domains = <&rpmpd QCM2290_VDDCX>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ dpu_intf1_out: endpoint { ++ remote-endpoint = <&mdss_dsi0_in>; ++ }; ++ }; ++ }; ++ ++ mdp_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-19200000 { ++ opp-hz = /bits/ 64 <19200000>; ++ required-opps = <&rpmpd_opp_min_svs>; ++ }; ++ ++ opp-192000000 { ++ opp-hz = /bits/ 64 <192000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ }; ++ ++ opp-256000000 { ++ opp-hz = /bits/ 64 <256000000>; ++ required-opps = <&rpmpd_opp_svs>; ++ }; ++ ++ opp-307200000 { ++ opp-hz = /bits/ 64 <307200000>; ++ required-opps = <&rpmpd_opp_svs_plus>; ++ }; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ required-opps = <&rpmpd_opp_nom>; ++ }; ++ }; ++ }; ++ ++ mdss_dsi0: dsi@5e94000 { ++ compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; ++ reg = <0x0 0x05e94000 0x0 0x400>; ++ reg-names = "dsi_ctrl"; ++ ++ interrupt-parent = <&mdss>; ++ interrupts = <4>; ++ ++ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, ++ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, ++ <&dispcc DISP_CC_MDSS_PCLK0_CLK>, ++ <&dispcc DISP_CC_MDSS_ESC0_CLK>, ++ <&dispcc DISP_CC_MDSS_AHB_CLK>, ++ <&gcc GCC_DISP_HF_AXI_CLK>; ++ clock-names = "byte", ++ "byte_intf", ++ "pixel", ++ "core", ++ "iface", ++ "bus"; ++ ++ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, ++ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; ++ assigned-clock-parents = <&mdss_dsi0_phy 0>, ++ <&mdss_dsi0_phy 1>; ++ ++ operating-points-v2 = <&dsi_opp_table>; ++ power-domains = <&rpmpd QCM2290_VDDCX>; ++ phys = <&mdss_dsi0_phy>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ ++ dsi_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-19200000 { ++ opp-hz = /bits/ 64 <19200000>; ++ required-opps = <&rpmpd_opp_min_svs>; ++ }; ++ ++ opp-164000000 { ++ opp-hz = /bits/ 64 <164000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ }; ++ ++ opp-187500000 { ++ opp-hz = /bits/ 64 <187500000>; ++ required-opps = <&rpmpd_opp_svs>; ++ }; ++ }; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ mdss_dsi0_in: endpoint { ++ remote-endpoint = <&dpu_intf1_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ mdss_dsi0_out: endpoint { ++ }; ++ }; ++ }; ++ }; ++ ++ mdss_dsi0_phy: phy@5e94400 { ++ compatible = "qcom,dsi-phy-14nm-2290"; ++ reg = <0x0 0x05e94400 0x0 0x100>, ++ <0x0 0x05e94500 0x0 0x300>, ++ <0x0 0x05e94800 0x0 0x188>; ++ reg-names = "dsi_phy", ++ "dsi_phy_lane", ++ "dsi_pll"; ++ ++ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, ++ <&rpmcc RPM_SMD_XO_CLK_SRC>; ++ clock-names = "iface", ++ "ref"; ++ ++ power-domains = <&rpmpd QCM2290_VDDMX>; ++ required-opps = <&rpmpd_opp_nom>; ++ ++ #clock-cells = <1>; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ }; ++ ++ dispcc: clock-controller@5f00000 { ++ compatible = "qcom,qcm2290-dispcc"; ++ reg = <0x0 0x05f00000 0x0 0x20000>; ++ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, ++ <&rpmcc RPM_SMD_XO_A_CLK_SRC>, ++ <&gcc GCC_DISP_GPLL0_CLK_SRC>, ++ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, ++ <&mdss_dsi0_phy 0>, ++ <&mdss_dsi0_phy 1>; ++ clock-names = "bi_tcxo", ++ "bi_tcxo_ao", ++ "gcc_disp_gpll0_clk_src", ++ "gcc_disp_gpll0_div_clk_src", ++ "dsi0_phy_pll_out_byteclk", ++ "dsi0_phy_pll_out_dsiclk"; ++ #power-domain-cells = <1>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0009_arm64_dts_qcom_qcm2290_hook_up_interconnects.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0009_arm64_dts_qcom_qcm2290_hook_up_interconnects.patch new file mode 100644 index 0000000..69fb618 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0009_arm64_dts_qcom_qcm2290_hook_up_interconnects.patch @@ -0,0 +1,448 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qcm2290: Hook up interconnects +Date: Wed, 29 Nov 2023 15:44:06 +0100 + +Add interconnect provider nodes and hook up interconnects to consumer +devices, including bwmon. + +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 5b970ff0193d67da4a8d2d5fda50dd8ddb50a71e] +--- + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 248 ++++++++++++++++++++++++++++++++++ + 1 file changed, 248 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +index a3edc4667cc5..ce04d0acdede 100644 +--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi ++++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi +@@ -12,6 +12,8 @@ + #include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> ++#include <dt-bindings/interconnect/qcom,qcm2290.h> ++#include <dt-bindings/interconnect/qcom,rpm-icc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + / { +@@ -151,6 +153,8 @@ scm: scm { + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; ++ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + }; + }; + +@@ -669,6 +673,33 @@ usb_qmpphy: phy@1615000 { + status = "disabled"; + }; + ++ system_noc: interconnect@1880000 { ++ compatible = "qcom,qcm2290-snoc"; ++ reg = <0x0 0x01880000 0x0 0x60200>; ++ #interconnect-cells = <2>; ++ ++ qup_virt: interconnect-qup { ++ compatible = "qcom,qcm2290-qup-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmnrt_virt: interconnect-mmnrt { ++ compatible = "qcom,qcm2290-mmnrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmrt_virt: interconnect-mmrt { ++ compatible = "qcom,qcm2290-mmrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ }; ++ ++ config_noc: interconnect@1900000 { ++ compatible = "qcom,qcm2290-cnoc"; ++ reg = <0x0 0x01900000 0x0 0x8200>; ++ #interconnect-cells = <2>; ++ }; ++ + qfprom@1b44000 { + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; +@@ -681,6 +712,60 @@ qusb2_hstx_trim: hstx-trim@25b { + }; + }; + ++ pmu@1b8e300 { ++ compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; ++ reg = <0x0 0x01b8e300 0x0 0x600>; ++ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; ++ ++ operating-points-v2 = <&cpu_bwmon_opp_table>; ++ interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG ++ &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; ++ ++ cpu_bwmon_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-0 { ++ opp-peak-kBps = <(200 * 4 * 1000)>; ++ }; ++ ++ opp-1 { ++ opp-peak-kBps = <(300 * 4 * 1000)>; ++ }; ++ ++ opp-2 { ++ opp-peak-kBps = <(451 * 4 * 1000)>; ++ }; ++ ++ opp-3 { ++ opp-peak-kBps = <(547 * 4 * 1000)>; ++ }; ++ ++ opp-4 { ++ opp-peak-kBps = <(681 * 4 * 1000)>; ++ }; ++ ++ opp-5 { ++ opp-peak-kBps = <(768 * 4 * 1000)>; ++ }; ++ ++ opp-6 { ++ opp-peak-kBps = <(1017 * 4 * 1000)>; ++ }; ++ ++ opp-7 { ++ opp-peak-kBps = <(1353 * 4 * 1000)>; ++ }; ++ ++ opp-8 { ++ opp-peak-kBps = <(1555 * 4 * 1000)>; ++ }; ++ ++ opp-9 { ++ opp-peak-kBps = <(1804 * 4 * 1000)>; ++ }; ++ }; ++ }; ++ + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, +@@ -721,6 +806,12 @@ rng: rng@4453000 { + clock-names = "core"; + }; + ++ bimc: interconnect@4480000 { ++ compatible = "qcom,qcm2290-bimc"; ++ reg = <0x0 0x04480000 0x0 0x80000>; ++ #interconnect-cells = <2>; ++ }; ++ + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; +@@ -756,13 +847,45 @@ sdhc_1: mmc@4744000 { + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; ++ operating-points-v2 = <&sdhc1_opp_table>; + iommus = <&apps_smmu 0xc0 0x0>; ++ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <8>; + + status = "disabled"; ++ ++ sdhc1_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <102400 65000>; ++ }; ++ ++ opp-192000000 { ++ opp-hz = /bits/ 64 <192000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ required-opps = <&rpmpd_opp_svs_plus>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ }; + }; + + sdhc_2: mmc@4784000 { +@@ -786,6 +909,12 @@ sdhc_2: mmc@4784000 { + power-domains = <&rpmpd QCM2290_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0xa0 0x0>; ++ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; +@@ -799,11 +928,15 @@ sdhc2_opp_table: opp-table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <261438 150000>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_svs_plus>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <261438 300000>; + }; + }; + }; +@@ -851,6 +984,15 @@ i2c0: i2c@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -867,6 +1009,12 @@ spi0: spi@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -880,6 +1028,12 @@ uart0: serial@4a80000 { + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -894,6 +1048,15 @@ i2c1: i2c@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -910,6 +1073,12 @@ spi1: spi@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -926,6 +1095,15 @@ i2c2: i2c@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -942,6 +1120,12 @@ spi2: spi@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -958,6 +1142,15 @@ i2c3: i2c@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -974,6 +1167,12 @@ spi3: spi@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -990,6 +1189,15 @@ i2c4: i2c@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1006,6 +1214,12 @@ spi4: spi@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1019,6 +1233,12 @@ uart4: serial@4a90000 { + clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -1033,6 +1253,15 @@ i2c5: i2c@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1049,6 +1278,12 @@ spi5: spi@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1081,6 +1316,13 @@ usb: usb@4ef8800 { + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; ++ /* TODO: USB<->IPA path */ ++ interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; ++ interconnect-names = "usb-ddr", ++ "apps-usb"; + wakeup-source; + + #address-cells = <2>; +@@ -1127,6 +1369,12 @@ mdss: display-subsystem@5e00000 { + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; ++ interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG ++ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; + + #address-cells = <2>; + #size-cells = <2>; +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0010_arm64_dts_qcom_qrb2210_rb1_set_up_hdmi.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0010_arm64_dts_qcom_qrb2210_rb1_set_up_hdmi.patch new file mode 100644 index 0000000..d202ef7 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0010_arm64_dts_qcom_qrb2210_rb1_set_up_hdmi.patch @@ -0,0 +1,126 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: Set up HDMI +Date: Wed, 29 Nov 2023 15:44:07 +0100 + +Add the required nodes to support display output via the HDMI port. + +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 616eda24edd48b8b56516886c51d211fbfd2679b] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 86 ++++++++++++++++++++++++++++++++ + 1 file changed, 86 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index 94885b9c21c8..ac6584164058 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -40,6 +40,17 @@ key-volume-up { + }; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <<9611_out>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -158,6 +169,68 @@ vph_pwr: regulator-vph-pwr { + }; + }; + ++&gpi_dma0 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ status = "okay"; ++ ++ lt9611_codec: hdmi-bridge@2b { ++ compatible = "lontium,lt9611uxc"; ++ reg = <0x2b>; ++ interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; ++ reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; ++ ++ vdd-supply = <&vreg_hdmi_out_1p2>; ++ vcc-supply = <<9611_3v3>; ++ ++ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; ++ pinctrl-names = "default"; ++ #sound-dai-cells = <1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ lt9611_a: endpoint { ++ remote-endpoint = <&mdss_dsi0_out>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ lt9611_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&mdss { ++ status = "okay"; ++}; ++ ++&mdss_dsi0 { ++ vdda-supply = <&pm2250_l5>; ++ status = "okay"; ++}; ++ ++&mdss_dsi0_out { ++ remote-endpoint = <<9611_a>; ++ data-lanes = <0 1 2 3>; ++}; ++ ++&mdss_dsi0_phy { ++ status = "okay"; ++}; ++ + &pm2250_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +@@ -377,6 +450,19 @@ &sdhc_2 { + }; + + &tlmm { ++ lt9611_rst_pin: lt9611-rst-state { ++ pins = "gpio41"; ++ function = "gpio"; ++ input-disable; ++ output-high; ++ }; ++ ++ lt9611_irq_pin: lt9611-irq-state { ++ pins = "gpio46"; ++ function = "gpio"; ++ bias-disable; ++ }; ++ + sd_det_in_on: sd-det-in-on-state { + pins = "gpio88"; + function = "gpio"; +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0011_arm64_dts_qcom_qrb2210_rb1_enable_can_bus_controller.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0011_arm64_dts_qcom_qrb2210_rb1_enable_can_bus_controller.patch new file mode 100644 index 0000000..485ec79 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0011_arm64_dts_qcom_qrb2210_rb1_enable_can_bus_controller.patch @@ -0,0 +1,54 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: Enable CAN bus controller +Date: Wed, 29 Nov 2023 15:44:08 +0100 + +Enable the Microchip mcp2518fd hosted on the SPI5 bus. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 252bc7ad359478dba8d77bce9502f2cc7bb547a3] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index ac6584164058..ac597eb3fe9d 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ clocks { ++ clk40M: can-clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; +@@ -449,6 +457,20 @@ &sdhc_2 { + status = "okay"; + }; + ++&spi5 { ++ status = "okay"; ++ ++ can@0 { ++ compatible = "microchip,mcp2518fd"; ++ reg = <0>; ++ interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&clk40M>; ++ spi-max-frequency = <10000000>; ++ vdd-supply = <&vdc_5v>; ++ xceiver-supply = <&vdc_5v>; ++ }; ++}; ++ + &tlmm { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0012_arm64_dts_qcom_qrb2210_rb1_add_wifi_variant_property.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0012_arm64_dts_qcom_qrb2210_rb1_add_wifi_variant_property.patch new file mode 100644 index 0000000..4c5d177 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/features/0012_arm64_dts_qcom_qrb2210_rb1_add_wifi_variant_property.patch @@ -0,0 +1,47 @@ +From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: add wifi variant property +Date: Wed, 29 Nov 2023 15:44:09 +0100 + +The RB1 platform doesn't have board-specific board-id programmed, it uses +generic 0xff. Thus add the property with the 'variant' of the +calibration data. + +Note: the driver will check for the calibration data for the following +IDs, so existing board-2.bin files will continue to work. + +- 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120,variant=Thundercomm_RB1' +- 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120' +- 'bus=snoc,qmi-board-id=ff' + +For the reference, the board is identified by the driver in the +following way: + +ath10k_snoc c800000.wifi: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 +ath10k_snoc c800000.wifi: qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 +ath10k_snoc c800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 +ath10k_snoc c800000.wifi: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 +ath10k_snoc c800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 +ath10k_snoc c800000.wifi: htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 + +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git b6a56a5a25d6273729b2b5139d58e3d390318ed2] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index ac597eb3fe9d..bd7bcf803654 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -535,6 +535,7 @@ &wifi { + vdd-1.8-xo-supply = <&pm2250_l13>; + vdd-1.3-rfa-supply = <&pm2250_l10>; + vdd-3.3-ch0-supply = <&pm2250_l22>; ++ qcom,ath10k-calibration-variant = "Thundercomm_RB1"; + status = "okay"; + }; + +-- +2.43.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0001-arm64-dts-qcom-qrb2210-rb1-use-USB-host-mode.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0001-arm64-dts-qcom-qrb2210-rb1-use-USB-host-mode.patch new file mode 100644 index 0000000..4765451 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0001-arm64-dts-qcom-qrb2210-rb1-use-USB-host-mode.patch @@ -0,0 +1,41 @@ +From e0cee8dc6757f9f18718eec553be9fffa503e103 Mon Sep 17 00:00:00 2001 +From: Caleb Connolly <caleb.connolly@linaro.org> +Date: Wed, 25 Oct 2023 12:58:00 +0100 +Subject: [PATCH] arm64: dts: qcom: qrb2210-rb1: use USB host mode + +The default for the QCM2290 platform that this board is based on is OTG +mode, however the role detection logic is not hooked up for this board +and the dwc3 driver is configured to not allow role switching from +userspace. + +Force this board to host mode as this is the preferred usecase until we +get role switching hooked up. + +Fixes: e18771961336 ("arm64: dts: qcom: Add initial QTI RB1 device tree") +Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> +Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231025-b4-rb1-usb-host-v1-1-522616c575ef@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git e0cee8dc6757f9f18718eec553be9fffa503e103] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index bd7bcf803654..aa53b6af6d9c 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -523,6 +523,10 @@ &usb_qmpphy { + status = "okay"; + }; + ++&usb_dwc3 { ++ dr_mode = "host"; ++}; ++ + &usb_hsphy { + vdd-supply = <&pm2250_l12>; + vdda-pll-supply = <&pm2250_l13>; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0003_arm64_dts_qcom_qrb2210_rb1_enable_remote_processors.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0003_arm64_dts_qcom_qrb2210_rb1_enable_remote_processors.patch new file mode 100644 index 0000000..8161c44 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0003_arm64_dts_qcom_qrb2210_rb1_enable_remote_processors.patch @@ -0,0 +1,55 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: Enable remote processors +Date: Wed, 06 Sep 2023 11:24:57 +0200 + +Enable the ADSP, MPSS and Wi-Fi. Tighten up the Wi-Fi regulators to +make them compliant with that the chip expects. + +The Wi-Fi reports: +qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 9692ccc49583cd43184ea192af127635877e0f24] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index 0f7c59187896..5f7619518deb 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -134,6 +134,16 @@ &qupv3_id_0 { + status = "okay"; + }; + ++&remoteproc_adsp { ++ firmware-name = "qcom/qcm2290/adsp.mbn"; ++ status = "okay"; ++}; ++ ++&remoteproc_mpss { ++ firmware-name = "qcom/qcm2290/modem.mbn"; ++ status = "okay"; ++}; ++ + &rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; +@@ -373,6 +383,14 @@ &usb_hsphy { + status = "okay"; + }; + ++&wifi { ++ vdd-0.8-cx-mx-supply = <&pm2250_l7>; ++ vdd-1.8-xo-supply = <&pm2250_l13>; ++ vdd-1.3-rfa-supply = <&pm2250_l10>; ++ vdd-3.3-ch0-supply = <&pm2250_l22>; ++ status = "okay"; ++}; ++ + &xo_board { + clock-frequency = <38400000>; + }; +-- +2.42.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0004_arm64_dts_qcom_qrb2210_rb1_add_gpio_leds.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0004_arm64_dts_qcom_qrb2210_rb1_add_gpio_leds.patch new file mode 100644 index 0000000..933d410 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0004_arm64_dts_qcom_qrb2210_rb1_add_gpio_leds.patch @@ -0,0 +1,65 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: Add GPIO LEDs +Date: Wed, 06 Sep 2023 11:24:58 +0200 + +Add the three LEDs (blue/yellow/green) connected to TLMM GPIOs. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 02a2fcfbb835bac0c523b3f89326bc1c69f83ce0] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 33 ++++++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index 5f7619518deb..fd45f58e254d 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -5,6 +5,7 @@ + + /dts-v1/; + ++#include <dt-bindings/leds/common.h> + #include "qcm2290.dtsi" + #include "pm2250.dtsi" + +@@ -39,6 +40,38 @@ key-volume-up { + }; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-bt { ++ label = "blue:bt"; ++ function = LED_FUNCTION_BLUETOOTH; ++ color = <LED_COLOR_ID_BLUE>; ++ gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "bluetooth-power"; ++ default-state = "off"; ++ }; ++ ++ led-user0 { ++ label = "green:user0"; ++ function = LED_FUNCTION_INDICATOR; ++ color = <LED_COLOR_ID_GREEN>; ++ gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ default-state = "off"; ++ panic-indicator; ++ }; ++ ++ led-wlan { ++ label = "yellow:wlan"; ++ function = LED_FUNCTION_WLAN; ++ color = <LED_COLOR_ID_YELLOW>; ++ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "phy0tx"; ++ default-state = "off"; ++ }; ++ }; ++ + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { + compatible = "regulator-fixed"; + regulator-name = "VREG_HDMI_OUT_1P2"; +-- +2.42.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0005_arm64_dts_qcom_qrb2210_rb1_hook_up_usb3.patch b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0005_arm64_dts_qcom_qrb2210_rb1_hook_up_usb3.patch new file mode 100644 index 0000000..6f93da3 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb2210-dts/sans-icc/0005_arm64_dts_qcom_qrb2210_rb1_hook_up_usb3.patch @@ -0,0 +1,32 @@ +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Subject: arm64: dts: qcom: qrb2210-rb1: Hook up USB3 +Date: Wed, 06 Sep 2023 11:24:59 +0200 + +Configure the USB3 PHY to enable USB3 functionality + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 59f9ff79cd9cf3bc10743d61662b5729fcffff24] +--- + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +index fd45f58e254d..94885b9c21c8 100644 +--- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts ++++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +@@ -409,6 +409,12 @@ &usb { + status = "okay"; + }; + ++&usb_qmpphy { ++ vdda-phy-supply = <&pm2250_l12>; ++ vdda-pll-supply = <&pm2250_l13>; ++ status = "okay"; ++}; ++ + &usb_hsphy { + vdd-supply = <&pm2250_l12>; + vdda-pll-supply = <&pm2250_l13>; +-- +2.42.0 diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-dt-bindings-interconnect-Add-Qualcomm-SM6115-NoC.patch b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-dt-bindings-interconnect-Add-Qualcomm-SM6115-NoC.patch new file mode 100644 index 0000000..94565eb --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-dt-bindings-interconnect-Add-Qualcomm-SM6115-NoC.patch @@ -0,0 +1,297 @@ +From 658902913c7044ac5d56b14cea54e735a071fe41 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Wed, 29 Nov 2023 15:41:01 +0100 +Subject: [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM6115 NoC + +Add bindings for Qualcomm SM6115 Network-On-Chip interconnect. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Link: https://lore.kernel.org/r/20231125-topic-6115icc-v3-1-bd8907b8cfd7@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 658902913c7044ac5d56b14cea54e735a071fe41] +--- + .../bindings/interconnect/qcom,sm6115.yaml | 152 ++++++++++++++++++ + .../dt-bindings/interconnect/qcom,sm6115.h | 111 +++++++++++++ + 2 files changed, 263 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml + create mode 100644 include/dt-bindings/interconnect/qcom,sm6115.h + +diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml +new file mode 100644 +index 000000000000..14b1a0b08e73 +--- /dev/null ++++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml +@@ -0,0 +1,152 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm SM6115 Network-On-Chip interconnect ++ ++maintainers: ++ - Konrad Dybcio <konradybcio@kernel.org> ++ ++description: ++ The Qualcomm SM6115 interconnect providers support adjusting the ++ bandwidth requirements between the various NoC fabrics. ++ ++properties: ++ compatible: ++ enum: ++ - qcom,sm6115-bimc ++ - qcom,sm6115-cnoc ++ - qcom,sm6115-snoc ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ maxItems: 4 ++ ++ clock-names: ++ minItems: 1 ++ maxItems: 4 ++ ++# Child node's properties ++patternProperties: ++ '^interconnect-[a-z0-9]+$': ++ type: object ++ description: ++ The interconnect providers do not have a separate QoS register space, ++ but share parent's space. ++ ++ $ref: qcom,rpm-common.yaml# ++ ++ properties: ++ compatible: ++ enum: ++ - qcom,sm6115-clk-virt ++ - qcom,sm6115-mmrt-virt ++ - qcom,sm6115-mmnrt-virt ++ ++ required: ++ - compatible ++ ++ unevaluatedProperties: false ++ ++required: ++ - compatible ++ - reg ++ ++allOf: ++ - $ref: qcom,rpm-common.yaml# ++ - if: ++ properties: ++ compatible: ++ const: qcom,sm6115-cnoc ++ ++ then: ++ properties: ++ clocks: ++ items: ++ - description: USB-NoC AXI clock ++ ++ clock-names: ++ items: ++ - const: usb_axi ++ ++ - if: ++ properties: ++ compatible: ++ const: qcom,sm6115-snoc ++ ++ then: ++ properties: ++ clocks: ++ items: ++ - description: CPU-NoC AXI clock. ++ - description: UFS-NoC AXI clock. ++ - description: USB-NoC AXI clock. ++ - description: IPA clock. ++ ++ clock-names: ++ items: ++ - const: cpu_axi ++ - const: ufs_axi ++ - const: usb_axi ++ - const: ipa ++ ++ - if: ++ properties: ++ compatible: ++ enum: ++ - qcom,sm6115-bimc ++ - qcom,sm6115-clk-virt ++ - qcom,sm6115-mmrt-virt ++ - qcom,sm6115-mmnrt-virt ++ ++ then: ++ properties: ++ clocks: false ++ clock-names: false ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include <dt-bindings/clock/qcom,gcc-sm6115.h> ++ #include <dt-bindings/clock/qcom,rpmcc.h> ++ ++ snoc: interconnect@1880000 { ++ compatible = "qcom,sm6115-snoc"; ++ reg = <0x01880000 0x60200>; ++ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, ++ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, ++ <&rpmcc RPM_SMD_IPA_CLK>; ++ clock-names = "cpu_axi", ++ "ufs_axi", ++ "usb_axi", ++ "ipa"; ++ #interconnect-cells = <1>; ++ ++ qup_virt: interconnect-clk { ++ compatible = "qcom,sm6115-clk-virt"; ++ #interconnect-cells = <1>; ++ }; ++ ++ mmnrt_virt: interconnect-mmnrt { ++ compatible = "qcom,sm6115-mmnrt-virt"; ++ #interconnect-cells = <1>; ++ }; ++ ++ mmrt_virt: interconnect-mmrt { ++ compatible = "qcom,sm6115-mmrt-virt"; ++ #interconnect-cells = <1>; ++ }; ++ }; ++ ++ cnoc: interconnect@1900000 { ++ compatible = "qcom,sm6115-cnoc"; ++ reg = <0x01900000 0x8200>; ++ #interconnect-cells = <1>; ++ }; +diff --git a/include/dt-bindings/interconnect/qcom,sm6115.h b/include/dt-bindings/interconnect/qcom,sm6115.h +new file mode 100644 +index 000000000000..21090e585f05 +--- /dev/null ++++ b/include/dt-bindings/interconnect/qcom,sm6115.h +@@ -0,0 +1,111 @@ ++/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ ++/* ++ * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023, Linaro Limited ++ */ ++ ++#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H ++#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H ++ ++/* BIMC */ ++#define MASTER_AMPSS_M0 0 ++#define MASTER_SNOC_BIMC_RT 1 ++#define MASTER_SNOC_BIMC_NRT 2 ++#define SNOC_BIMC_MAS 3 ++#define MASTER_GRAPHICS_3D 4 ++#define MASTER_TCU_0 5 ++#define SLAVE_EBI_CH0 6 ++#define BIMC_SNOC_SLV 7 ++ ++/* CNOC */ ++#define SNOC_CNOC_MAS 0 ++#define MASTER_QDSS_DAP 1 ++#define SLAVE_AHB2PHY_USB 2 ++#define SLAVE_APSS_THROTTLE_CFG 3 ++#define SLAVE_BIMC_CFG 4 ++#define SLAVE_BOOT_ROM 5 ++#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 ++#define SLAVE_CAMERA_RT_THROTTLE_CFG 7 ++#define SLAVE_CAMERA_CFG 8 ++#define SLAVE_CLK_CTL 9 ++#define SLAVE_RBCPR_CX_CFG 10 ++#define SLAVE_RBCPR_MX_CFG 11 ++#define SLAVE_CRYPTO_0_CFG 12 ++#define SLAVE_DCC_CFG 13 ++#define SLAVE_DDR_PHY_CFG 14 ++#define SLAVE_DDR_SS_CFG 15 ++#define SLAVE_DISPLAY_CFG 16 ++#define SLAVE_DISPLAY_THROTTLE_CFG 17 ++#define SLAVE_GPU_CFG 18 ++#define SLAVE_GPU_THROTTLE_CFG 19 ++#define SLAVE_HWKM_CORE 20 ++#define SLAVE_IMEM_CFG 21 ++#define SLAVE_IPA_CFG 22 ++#define SLAVE_LPASS 23 ++#define SLAVE_MAPSS 24 ++#define SLAVE_MDSP_MPU_CFG 25 ++#define SLAVE_MESSAGE_RAM 26 ++#define SLAVE_CNOC_MSS 27 ++#define SLAVE_PDM 28 ++#define SLAVE_PIMEM_CFG 29 ++#define SLAVE_PKA_CORE 30 ++#define SLAVE_PMIC_ARB 31 ++#define SLAVE_QDSS_CFG 32 ++#define SLAVE_QM_CFG 33 ++#define SLAVE_QM_MPU_CFG 34 ++#define SLAVE_QPIC 35 ++#define SLAVE_QUP_0 36 ++#define SLAVE_RPM 37 ++#define SLAVE_SDCC_1 38 ++#define SLAVE_SDCC_2 39 ++#define SLAVE_SECURITY 40 ++#define SLAVE_SNOC_CFG 41 ++#define SLAVE_TCSR 42 ++#define SLAVE_TLMM 43 ++#define SLAVE_USB3 44 ++#define SLAVE_VENUS_CFG 45 ++#define SLAVE_VENUS_THROTTLE_CFG 46 ++#define SLAVE_VSENSE_CTRL_CFG 47 ++#define SLAVE_SERVICE_CNOC 48 ++ ++/* SNOC */ ++#define MASTER_CRYPTO_CORE0 0 ++#define MASTER_SNOC_CFG 1 ++#define MASTER_TIC 2 ++#define MASTER_ANOC_SNOC 3 ++#define BIMC_SNOC_MAS 4 ++#define MASTER_PIMEM 5 ++#define MASTER_QDSS_BAM 6 ++#define MASTER_QPIC 7 ++#define MASTER_QUP_0 8 ++#define MASTER_IPA 9 ++#define MASTER_QDSS_ETR 10 ++#define MASTER_SDCC_1 11 ++#define MASTER_SDCC_2 12 ++#define MASTER_USB3 13 ++#define SLAVE_APPSS 14 ++#define SNOC_CNOC_SLV 15 ++#define SLAVE_OCIMEM 16 ++#define SLAVE_PIMEM 17 ++#define SNOC_BIMC_SLV 18 ++#define SLAVE_SERVICE_SNOC 19 ++#define SLAVE_QDSS_STM 20 ++#define SLAVE_TCU 21 ++#define SLAVE_ANOC_SNOC 22 ++ ++/* CLK Virtual */ ++#define MASTER_QUP_CORE_0 0 ++#define SLAVE_QUP_CORE_0 1 ++ ++/* MMRT Virtual */ ++#define MASTER_CAMNOC_HF 0 ++#define MASTER_MDP_PORT0 1 ++#define SLAVE_SNOC_BIMC_RT 2 ++ ++/* MMNRT Virtual */ ++#define MASTER_CAMNOC_SF 0 ++#define MASTER_VIDEO_P0 1 ++#define MASTER_VIDEO_PROC 2 ++#define SLAVE_SNOC_BIMC_NRT 3 ++ ++#endif +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-iommu-arm-smmu-qcom-Add-SM6115-MDSS-compatible.patch b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-iommu-arm-smmu-qcom-Add-SM6115-MDSS-compatible.patch new file mode 100644 index 0000000..6686e98 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0001-iommu-arm-smmu-qcom-Add-SM6115-MDSS-compatible.patch @@ -0,0 +1,30 @@ +From 3b744008c1d08c25c9066206b8f4c3fb0006e9d0 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Wed, 29 Nov 2023 15:44:02 +0100 +Subject: [PATCH] iommu/arm-smmu-qcom: Add SM6115 MDSS compatible + +Add the SM6115 MDSS compatible to clients compatible list, as it also +needs the workarounds. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Upstream-Status: Pending +--- + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +index fdabb4b3f7c0..db7c4c71dec1 100644 +--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c ++++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +@@ -254,6 +254,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { + { .compatible = "qcom,sc8280xp-mdss" }, + { .compatible = "qcom,sdm845-mdss" }, + { .compatible = "qcom,sdm845-mss-pil" }, ++ { .compatible = "qcom,sm6115-mdss" }, + { .compatible = "qcom,sm6350-mdss" }, + { .compatible = "qcom,sm6375-mdss" }, + { .compatible = "qcom,sm8150-mdss" }, +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0002-interconnect-qcom-Add-SM6115-interconnect-provider-d.patch b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0002-interconnect-qcom-Add-SM6115-interconnect-provider-d.patch new file mode 100644 index 0000000..ad75aa3 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-drivers/icc/0002-interconnect-qcom-Add-SM6115-interconnect-provider-d.patch @@ -0,0 +1,1495 @@ +From 2eab57b131bd9ef22377e09de43beb45a650a752 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Wed, 29 Nov 2023 15:41:02 +0100 +Subject: [PATCH 2/2] interconnect: qcom: Add SM6115 interconnect provider + driver + +Add a driver for managing NoC providers on SM6115. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231125-topic-6115icc-v3-2-bd8907b8cfd7@linaro.org +Signed-off-by: Georgi Djakov <djakov@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 2eab57b131bd9ef22377e09de43beb45a650a752] +--- + drivers/interconnect/qcom/Kconfig | 9 + + drivers/interconnect/qcom/Makefile | 2 + + drivers/interconnect/qcom/sm6115.c | 1427 ++++++++++++++++++++++++++++ + 3 files changed, 1438 insertions(+) + create mode 100644 drivers/interconnect/qcom/sm6115.c + +diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig +index 62b516d38d03..d2a54c5ecd06 100644 +--- a/drivers/interconnect/qcom/Kconfig ++++ b/drivers/interconnect/qcom/Kconfig +@@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65 + This is a driver for the Qualcomm Network-on-Chip on sdx65-based + platforms. + ++config INTERCONNECT_QCOM_SM6115 ++ tristate "Qualcomm SM6115 interconnect driver" ++ depends on INTERCONNECT_QCOM ++ depends on QCOM_SMD_RPM ++ select INTERCONNECT_QCOM_SMD_RPM ++ help ++ This is a driver for the Qualcomm Network-on-Chip on sm6115-based ++ platforms. ++ + config INTERCONNECT_QCOM_SM6350 + tristate "Qualcomm SM6350 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE +diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile +index c5320e293960..7564042a30dc 100644 +--- a/drivers/interconnect/qcom/Makefile ++++ b/drivers/interconnect/qcom/Makefile +@@ -24,6 +24,7 @@ qnoc-sdm845-objs := sdm845.o + qnoc-sdm845-objs := sdm845.o + qnoc-sdx55-objs := sdx55.o + qnoc-sdx65-objs := sdx65.o ++qnoc-sm6115-objs := sm6115.o + qnoc-sm6350-objs := sm6350.o + qnoc-sm8150-objs := sm8150.o + qnoc-sm8250-objs := sm8250.o +@@ -53,6 +54,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o + obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o + obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o + obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o ++obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o + obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o + obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o + obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o +diff --git a/drivers/interconnect/qcom/sm6115.c b/drivers/interconnect/qcom/sm6115.c +new file mode 100644 +index 000000000000..c49a83c87739 +--- /dev/null ++++ b/drivers/interconnect/qcom/sm6115.c +@@ -0,0 +1,1427 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023, Linaro Limited ++ */ ++ ++#include <dt-bindings/interconnect/qcom,sm6115.h> ++#include <linux/clk.h> ++#include <linux/device.h> ++#include <linux/interconnect-provider.h> ++#include <linux/io.h> ++#include <linux/module.h> ++#include <linux/of_device.h> ++#include <linux/of_platform.h> ++#include <linux/platform_device.h> ++#include <linux/regmap.h> ++#include <linux/slab.h> ++ ++#include "icc-rpm.h" ++ ++static const char * const snoc_intf_clocks[] = { ++ "cpu_axi", ++ "ufs_axi", ++ "usb_axi", ++ "ipa", /* Required by qxm_ipa */ ++}; ++ ++static const char * const cnoc_intf_clocks[] = { ++ "usb_axi", ++}; ++ ++enum { ++ SM6115_MASTER_AMPSS_M0, ++ SM6115_MASTER_ANOC_SNOC, ++ SM6115_MASTER_BIMC_SNOC, ++ SM6115_MASTER_CAMNOC_HF, ++ SM6115_MASTER_CAMNOC_SF, ++ SM6115_MASTER_CRYPTO_CORE0, ++ SM6115_MASTER_GRAPHICS_3D, ++ SM6115_MASTER_IPA, ++ SM6115_MASTER_MDP_PORT0, ++ SM6115_MASTER_PIMEM, ++ SM6115_MASTER_QDSS_BAM, ++ SM6115_MASTER_QDSS_DAP, ++ SM6115_MASTER_QDSS_ETR, ++ SM6115_MASTER_QPIC, ++ SM6115_MASTER_QUP_0, ++ SM6115_MASTER_QUP_CORE_0, ++ SM6115_MASTER_SDCC_1, ++ SM6115_MASTER_SDCC_2, ++ SM6115_MASTER_SNOC_BIMC_NRT, ++ SM6115_MASTER_SNOC_BIMC_RT, ++ SM6115_MASTER_SNOC_BIMC, ++ SM6115_MASTER_SNOC_CFG, ++ SM6115_MASTER_SNOC_CNOC, ++ SM6115_MASTER_TCU_0, ++ SM6115_MASTER_TIC, ++ SM6115_MASTER_USB3, ++ SM6115_MASTER_VIDEO_P0, ++ SM6115_MASTER_VIDEO_PROC, ++ ++ SM6115_SLAVE_AHB2PHY_USB, ++ SM6115_SLAVE_ANOC_SNOC, ++ SM6115_SLAVE_APPSS, ++ SM6115_SLAVE_APSS_THROTTLE_CFG, ++ SM6115_SLAVE_BIMC_CFG, ++ SM6115_SLAVE_BIMC_SNOC, ++ SM6115_SLAVE_BOOT_ROM, ++ SM6115_SLAVE_CAMERA_CFG, ++ SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, ++ SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, ++ SM6115_SLAVE_CLK_CTL, ++ SM6115_SLAVE_CNOC_MSS, ++ SM6115_SLAVE_CRYPTO_0_CFG, ++ SM6115_SLAVE_DCC_CFG, ++ SM6115_SLAVE_DDR_PHY_CFG, ++ SM6115_SLAVE_DDR_SS_CFG, ++ SM6115_SLAVE_DISPLAY_CFG, ++ SM6115_SLAVE_DISPLAY_THROTTLE_CFG, ++ SM6115_SLAVE_EBI_CH0, ++ SM6115_SLAVE_GPU_CFG, ++ SM6115_SLAVE_GPU_THROTTLE_CFG, ++ SM6115_SLAVE_HWKM_CORE, ++ SM6115_SLAVE_IMEM_CFG, ++ SM6115_SLAVE_IPA_CFG, ++ SM6115_SLAVE_LPASS, ++ SM6115_SLAVE_MAPSS, ++ SM6115_SLAVE_MDSP_MPU_CFG, ++ SM6115_SLAVE_MESSAGE_RAM, ++ SM6115_SLAVE_OCIMEM, ++ SM6115_SLAVE_PDM, ++ SM6115_SLAVE_PIMEM_CFG, ++ SM6115_SLAVE_PIMEM, ++ SM6115_SLAVE_PKA_CORE, ++ SM6115_SLAVE_PMIC_ARB, ++ SM6115_SLAVE_QDSS_CFG, ++ SM6115_SLAVE_QDSS_STM, ++ SM6115_SLAVE_QM_CFG, ++ SM6115_SLAVE_QM_MPU_CFG, ++ SM6115_SLAVE_QPIC, ++ SM6115_SLAVE_QUP_0, ++ SM6115_SLAVE_QUP_CORE_0, ++ SM6115_SLAVE_RBCPR_CX_CFG, ++ SM6115_SLAVE_RBCPR_MX_CFG, ++ SM6115_SLAVE_RPM, ++ SM6115_SLAVE_SDCC_1, ++ SM6115_SLAVE_SDCC_2, ++ SM6115_SLAVE_SECURITY, ++ SM6115_SLAVE_SERVICE_CNOC, ++ SM6115_SLAVE_SERVICE_SNOC, ++ SM6115_SLAVE_SNOC_BIMC_NRT, ++ SM6115_SLAVE_SNOC_BIMC_RT, ++ SM6115_SLAVE_SNOC_BIMC, ++ SM6115_SLAVE_SNOC_CFG, ++ SM6115_SLAVE_SNOC_CNOC, ++ SM6115_SLAVE_TCSR, ++ SM6115_SLAVE_TCU, ++ SM6115_SLAVE_TLMM, ++ SM6115_SLAVE_USB3, ++ SM6115_SLAVE_VENUS_CFG, ++ SM6115_SLAVE_VENUS_THROTTLE_CFG, ++ SM6115_SLAVE_VSENSE_CTRL_CFG, ++}; ++ ++static const u16 slv_ebi_slv_bimc_snoc_links[] = { ++ SM6115_SLAVE_EBI_CH0, ++ SM6115_SLAVE_BIMC_SNOC, ++}; ++ ++static struct qcom_icc_node apps_proc = { ++ .name = "apps_proc", ++ .id = SM6115_MASTER_AMPSS_M0, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 0, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.prio_level = 0, ++ .qos.areq_prio = 0, ++ .mas_rpm_id = 0, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), ++ .links = slv_ebi_slv_bimc_snoc_links, ++}; ++ ++static const u16 link_slv_ebi[] = { ++ SM6115_SLAVE_EBI_CH0, ++}; ++ ++static struct qcom_icc_node mas_snoc_bimc_rt = { ++ .name = "mas_snoc_bimc_rt", ++ .id = SM6115_MASTER_SNOC_BIMC_RT, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 2, ++ .qos.qos_mode = NOC_QOS_MODE_BYPASS, ++ .qos.areq_prio = 0, ++ .qos.prio_level = 0, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_ebi), ++ .links = link_slv_ebi, ++}; ++ ++static struct qcom_icc_node mas_snoc_bimc_nrt = { ++ .name = "mas_snoc_bimc_nrt", ++ .id = SM6115_MASTER_SNOC_BIMC_NRT, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 3, ++ .qos.qos_mode = NOC_QOS_MODE_BYPASS, ++ .qos.areq_prio = 0, ++ .qos.prio_level = 0, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_ebi), ++ .links = link_slv_ebi, ++}; ++ ++static struct qcom_icc_node mas_snoc_bimc = { ++ .name = "mas_snoc_bimc", ++ .id = SM6115_MASTER_SNOC_BIMC, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 6, ++ .qos.qos_mode = NOC_QOS_MODE_BYPASS, ++ .qos.areq_prio = 0, ++ .qos.prio_level = 0, ++ .mas_rpm_id = 3, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_ebi), ++ .links = link_slv_ebi, ++}; ++ ++static struct qcom_icc_node qnm_gpu = { ++ .name = "qnm_gpu", ++ .id = SM6115_MASTER_GRAPHICS_3D, ++ .channels = 1, ++ .buswidth = 32, ++ .qos.qos_port = 1, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.prio_level = 0, ++ .qos.areq_prio = 0, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), ++ .links = slv_ebi_slv_bimc_snoc_links, ++}; ++ ++static struct qcom_icc_node tcu_0 = { ++ .name = "tcu_0", ++ .id = SM6115_MASTER_TCU_0, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 4, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.prio_level = 6, ++ .qos.areq_prio = 6, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), ++ .links = slv_ebi_slv_bimc_snoc_links, ++}; ++ ++static const u16 qup_core_0_links[] = { ++ SM6115_SLAVE_QUP_CORE_0, ++}; ++ ++static struct qcom_icc_node qup0_core_master = { ++ .name = "qup0_core_master", ++ .id = SM6115_MASTER_QUP_CORE_0, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = 170, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(qup_core_0_links), ++ .links = qup_core_0_links, ++}; ++ ++static const u16 link_slv_anoc_snoc[] = { ++ SM6115_SLAVE_ANOC_SNOC, ++}; ++ ++static struct qcom_icc_node crypto_c0 = { ++ .name = "crypto_c0", ++ .id = SM6115_MASTER_CRYPTO_CORE0, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 43, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = 23, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static const u16 mas_snoc_cnoc_links[] = { ++ SM6115_SLAVE_AHB2PHY_USB, ++ SM6115_SLAVE_APSS_THROTTLE_CFG, ++ SM6115_SLAVE_BIMC_CFG, ++ SM6115_SLAVE_BOOT_ROM, ++ SM6115_SLAVE_CAMERA_CFG, ++ SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, ++ SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, ++ SM6115_SLAVE_CLK_CTL, ++ SM6115_SLAVE_CNOC_MSS, ++ SM6115_SLAVE_CRYPTO_0_CFG, ++ SM6115_SLAVE_DCC_CFG, ++ SM6115_SLAVE_DDR_PHY_CFG, ++ SM6115_SLAVE_DDR_SS_CFG, ++ SM6115_SLAVE_DISPLAY_CFG, ++ SM6115_SLAVE_DISPLAY_THROTTLE_CFG, ++ SM6115_SLAVE_GPU_CFG, ++ SM6115_SLAVE_GPU_THROTTLE_CFG, ++ SM6115_SLAVE_HWKM_CORE, ++ SM6115_SLAVE_IMEM_CFG, ++ SM6115_SLAVE_IPA_CFG, ++ SM6115_SLAVE_LPASS, ++ SM6115_SLAVE_MAPSS, ++ SM6115_SLAVE_MDSP_MPU_CFG, ++ SM6115_SLAVE_MESSAGE_RAM, ++ SM6115_SLAVE_PDM, ++ SM6115_SLAVE_PIMEM_CFG, ++ SM6115_SLAVE_PKA_CORE, ++ SM6115_SLAVE_PMIC_ARB, ++ SM6115_SLAVE_QDSS_CFG, ++ SM6115_SLAVE_QM_CFG, ++ SM6115_SLAVE_QM_MPU_CFG, ++ SM6115_SLAVE_QPIC, ++ SM6115_SLAVE_QUP_0, ++ SM6115_SLAVE_RBCPR_CX_CFG, ++ SM6115_SLAVE_RBCPR_MX_CFG, ++ SM6115_SLAVE_RPM, ++ SM6115_SLAVE_SDCC_1, ++ SM6115_SLAVE_SDCC_2, ++ SM6115_SLAVE_SECURITY, ++ SM6115_SLAVE_SERVICE_CNOC, ++ SM6115_SLAVE_SNOC_CFG, ++ SM6115_SLAVE_TCSR, ++ SM6115_SLAVE_TLMM, ++ SM6115_SLAVE_USB3, ++ SM6115_SLAVE_VENUS_CFG, ++ SM6115_SLAVE_VENUS_THROTTLE_CFG, ++ SM6115_SLAVE_VSENSE_CTRL_CFG, ++}; ++ ++static struct qcom_icc_node mas_snoc_cnoc = { ++ .name = "mas_snoc_cnoc", ++ .id = SM6115_MASTER_SNOC_CNOC, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), ++ .links = mas_snoc_cnoc_links, ++}; ++ ++static struct qcom_icc_node xm_dap = { ++ .name = "xm_dap", ++ .id = SM6115_MASTER_QDSS_DAP, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), ++ .links = mas_snoc_cnoc_links, ++}; ++ ++static const u16 link_slv_snoc_bimc_nrt[] = { ++ SM6115_SLAVE_SNOC_BIMC_NRT, ++}; ++ ++static struct qcom_icc_node qnm_camera_nrt = { ++ .name = "qnm_camera_nrt", ++ .id = SM6115_MASTER_CAMNOC_SF, ++ .channels = 1, ++ .buswidth = 32, ++ .qos.qos_port = 25, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 3, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), ++ .links = link_slv_snoc_bimc_nrt, ++}; ++ ++static struct qcom_icc_node qxm_venus0 = { ++ .name = "qxm_venus0", ++ .id = SM6115_MASTER_VIDEO_P0, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 30, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 3, ++ .qos.urg_fwd_en = true, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), ++ .links = link_slv_snoc_bimc_nrt, ++}; ++ ++static struct qcom_icc_node qxm_venus_cpu = { ++ .name = "qxm_venus_cpu", ++ .id = SM6115_MASTER_VIDEO_PROC, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 34, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), ++ .links = link_slv_snoc_bimc_nrt, ++}; ++ ++static const u16 link_slv_snoc_bimc_rt[] = { ++ SM6115_SLAVE_SNOC_BIMC_RT, ++}; ++ ++static struct qcom_icc_node qnm_camera_rt = { ++ .name = "qnm_camera_rt", ++ .id = SM6115_MASTER_CAMNOC_HF, ++ .channels = 1, ++ .buswidth = 32, ++ .qos.qos_port = 31, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 3, ++ .qos.urg_fwd_en = true, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), ++ .links = link_slv_snoc_bimc_rt, ++}; ++ ++static struct qcom_icc_node qxm_mdp0 = { ++ .name = "qxm_mdp0", ++ .id = SM6115_MASTER_MDP_PORT0, ++ .channels = 1, ++ .buswidth = 16, ++ .qos.qos_port = 26, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 3, ++ .qos.urg_fwd_en = true, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), ++ .links = link_slv_snoc_bimc_rt, ++}; ++ ++static const u16 slv_service_snoc_links[] = { ++ SM6115_SLAVE_SERVICE_SNOC, ++}; ++ ++static struct qcom_icc_node qhm_snoc_cfg = { ++ .name = "qhm_snoc_cfg", ++ .id = SM6115_MASTER_SNOC_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_service_snoc_links), ++ .links = slv_service_snoc_links, ++}; ++ ++static const u16 mas_tic_links[] = { ++ SM6115_SLAVE_APPSS, ++ SM6115_SLAVE_OCIMEM, ++ SM6115_SLAVE_PIMEM, ++ SM6115_SLAVE_QDSS_STM, ++ SM6115_SLAVE_TCU, ++ SM6115_SLAVE_SNOC_BIMC, ++ SM6115_SLAVE_SNOC_CNOC, ++}; ++ ++static struct qcom_icc_node qhm_tic = { ++ .name = "qhm_tic", ++ .id = SM6115_MASTER_TIC, ++ .channels = 1, ++ .buswidth = 4, ++ .qos.qos_port = 29, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_tic_links), ++ .links = mas_tic_links, ++}; ++ ++static struct qcom_icc_node mas_anoc_snoc = { ++ .name = "mas_anoc_snoc", ++ .id = SM6115_MASTER_ANOC_SNOC, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_tic_links), ++ .links = mas_tic_links, ++}; ++ ++static const u16 mas_bimc_snoc_links[] = { ++ SM6115_SLAVE_APPSS, ++ SM6115_SLAVE_SNOC_CNOC, ++ SM6115_SLAVE_OCIMEM, ++ SM6115_SLAVE_PIMEM, ++ SM6115_SLAVE_QDSS_STM, ++ SM6115_SLAVE_TCU, ++}; ++ ++static struct qcom_icc_node mas_bimc_snoc = { ++ .name = "mas_bimc_snoc", ++ .id = SM6115_MASTER_BIMC_SNOC, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = 21, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_bimc_snoc_links), ++ .links = mas_bimc_snoc_links, ++}; ++ ++static const u16 mas_pimem_links[] = { ++ SM6115_SLAVE_OCIMEM, ++ SM6115_SLAVE_SNOC_BIMC, ++}; ++ ++static struct qcom_icc_node qxm_pimem = { ++ .name = "qxm_pimem", ++ .id = SM6115_MASTER_PIMEM, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 41, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(mas_pimem_links), ++ .links = mas_pimem_links, ++}; ++ ++static struct qcom_icc_node qhm_qdss_bam = { ++ .name = "qhm_qdss_bam", ++ .id = SM6115_MASTER_QDSS_BAM, ++ .channels = 1, ++ .buswidth = 4, ++ .qos.qos_port = 23, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node qhm_qpic = { ++ .name = "qhm_qpic", ++ .id = SM6115_MASTER_QPIC, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node qhm_qup0 = { ++ .name = "qhm_qup0", ++ .id = SM6115_MASTER_QUP_0, ++ .channels = 1, ++ .buswidth = 4, ++ .qos.qos_port = 21, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = 166, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node qxm_ipa = { ++ .name = "qxm_ipa", ++ .id = SM6115_MASTER_IPA, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 24, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = 59, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node xm_qdss_etr = { ++ .name = "xm_qdss_etr", ++ .id = SM6115_MASTER_QDSS_ETR, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 33, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node xm_sdc1 = { ++ .name = "xm_sdc1", ++ .id = SM6115_MASTER_SDCC_1, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 38, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = 33, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node xm_sdc2 = { ++ .name = "xm_sdc2", ++ .id = SM6115_MASTER_SDCC_2, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 44, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = 35, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node xm_usb3_0 = { ++ .name = "xm_usb3_0", ++ .id = SM6115_MASTER_USB3, ++ .channels = 1, ++ .buswidth = 8, ++ .qos.qos_port = 45, ++ .qos.qos_mode = NOC_QOS_MODE_FIXED, ++ .qos.areq_prio = 2, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), ++ .links = link_slv_anoc_snoc, ++}; ++ ++static struct qcom_icc_node ebi = { ++ .name = "ebi", ++ .id = SM6115_SLAVE_EBI_CH0, ++ .channels = 2, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 0, ++}; ++ ++static const u16 slv_bimc_snoc_links[] = { ++ SM6115_MASTER_BIMC_SNOC, ++}; ++ ++static struct qcom_icc_node slv_bimc_snoc = { ++ .name = "slv_bimc_snoc", ++ .id = SM6115_SLAVE_BIMC_SNOC, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 2, ++ .num_links = ARRAY_SIZE(slv_bimc_snoc_links), ++ .links = slv_bimc_snoc_links, ++}; ++ ++static struct qcom_icc_node qup0_core_slave = { ++ .name = "qup0_core_slave", ++ .id = SM6115_SLAVE_QUP_CORE_0, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_ahb2phy_usb = { ++ .name = "qhs_ahb2phy_usb", ++ .id = SM6115_SLAVE_AHB2PHY_USB, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_apss_throttle_cfg = { ++ .name = "qhs_apss_throttle_cfg", ++ .id = SM6115_SLAVE_APSS_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_bimc_cfg = { ++ .name = "qhs_bimc_cfg", ++ .id = SM6115_SLAVE_BIMC_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_boot_rom = { ++ .name = "qhs_boot_rom", ++ .id = SM6115_SLAVE_BOOT_ROM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { ++ .name = "qhs_camera_nrt_throttle_cfg", ++ .id = SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { ++ .name = "qhs_camera_rt_throttle_cfg", ++ .id = SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_camera_ss_cfg = { ++ .name = "qhs_camera_ss_cfg", ++ .id = SM6115_SLAVE_CAMERA_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_clk_ctl = { ++ .name = "qhs_clk_ctl", ++ .id = SM6115_SLAVE_CLK_CTL, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_cpr_cx = { ++ .name = "qhs_cpr_cx", ++ .id = SM6115_SLAVE_RBCPR_CX_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_cpr_mx = { ++ .name = "qhs_cpr_mx", ++ .id = SM6115_SLAVE_RBCPR_MX_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_crypto0_cfg = { ++ .name = "qhs_crypto0_cfg", ++ .id = SM6115_SLAVE_CRYPTO_0_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_dcc_cfg = { ++ .name = "qhs_dcc_cfg", ++ .id = SM6115_SLAVE_DCC_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_ddr_phy_cfg = { ++ .name = "qhs_ddr_phy_cfg", ++ .id = SM6115_SLAVE_DDR_PHY_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_ddr_ss_cfg = { ++ .name = "qhs_ddr_ss_cfg", ++ .id = SM6115_SLAVE_DDR_SS_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_disp_ss_cfg = { ++ .name = "qhs_disp_ss_cfg", ++ .id = SM6115_SLAVE_DISPLAY_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_display_throttle_cfg = { ++ .name = "qhs_display_throttle_cfg", ++ .id = SM6115_SLAVE_DISPLAY_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_gpu_cfg = { ++ .name = "qhs_gpu_cfg", ++ .id = SM6115_SLAVE_GPU_CFG, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_gpu_throttle_cfg = { ++ .name = "qhs_gpu_throttle_cfg", ++ .id = SM6115_SLAVE_GPU_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_hwkm = { ++ .name = "qhs_hwkm", ++ .id = SM6115_SLAVE_HWKM_CORE, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_imem_cfg = { ++ .name = "qhs_imem_cfg", ++ .id = SM6115_SLAVE_IMEM_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_ipa_cfg = { ++ .name = "qhs_ipa_cfg", ++ .id = SM6115_SLAVE_IPA_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_lpass = { ++ .name = "qhs_lpass", ++ .id = SM6115_SLAVE_LPASS, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_mapss = { ++ .name = "qhs_mapss", ++ .id = SM6115_SLAVE_MAPSS, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_mdsp_mpu_cfg = { ++ .name = "qhs_mdsp_mpu_cfg", ++ .id = SM6115_SLAVE_MDSP_MPU_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_mesg_ram = { ++ .name = "qhs_mesg_ram", ++ .id = SM6115_SLAVE_MESSAGE_RAM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_mss = { ++ .name = "qhs_mss", ++ .id = SM6115_SLAVE_CNOC_MSS, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_pdm = { ++ .name = "qhs_pdm", ++ .id = SM6115_SLAVE_PDM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_pimem_cfg = { ++ .name = "qhs_pimem_cfg", ++ .id = SM6115_SLAVE_PIMEM_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_pka_wrapper = { ++ .name = "qhs_pka_wrapper", ++ .id = SM6115_SLAVE_PKA_CORE, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_pmic_arb = { ++ .name = "qhs_pmic_arb", ++ .id = SM6115_SLAVE_PMIC_ARB, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_qdss_cfg = { ++ .name = "qhs_qdss_cfg", ++ .id = SM6115_SLAVE_QDSS_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_qm_cfg = { ++ .name = "qhs_qm_cfg", ++ .id = SM6115_SLAVE_QM_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_qm_mpu_cfg = { ++ .name = "qhs_qm_mpu_cfg", ++ .id = SM6115_SLAVE_QM_MPU_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_qpic = { ++ .name = "qhs_qpic", ++ .id = SM6115_SLAVE_QPIC, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_qup0 = { ++ .name = "qhs_qup0", ++ .id = SM6115_SLAVE_QUP_0, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_rpm = { ++ .name = "qhs_rpm", ++ .id = SM6115_SLAVE_RPM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_sdc1 = { ++ .name = "qhs_sdc1", ++ .id = SM6115_SLAVE_SDCC_1, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_sdc2 = { ++ .name = "qhs_sdc2", ++ .id = SM6115_SLAVE_SDCC_2, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_security = { ++ .name = "qhs_security", ++ .id = SM6115_SLAVE_SECURITY, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static const u16 slv_snoc_cfg_links[] = { ++ SM6115_MASTER_SNOC_CFG, ++}; ++ ++static struct qcom_icc_node qhs_snoc_cfg = { ++ .name = "qhs_snoc_cfg", ++ .id = SM6115_SLAVE_SNOC_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_snoc_cfg_links), ++ .links = slv_snoc_cfg_links, ++}; ++ ++static struct qcom_icc_node qhs_tcsr = { ++ .name = "qhs_tcsr", ++ .id = SM6115_SLAVE_TCSR, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_tlmm = { ++ .name = "qhs_tlmm", ++ .id = SM6115_SLAVE_TLMM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_usb3 = { ++ .name = "qhs_usb3", ++ .id = SM6115_SLAVE_USB3, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_venus_cfg = { ++ .name = "qhs_venus_cfg", ++ .id = SM6115_SLAVE_VENUS_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_venus_throttle_cfg = { ++ .name = "qhs_venus_throttle_cfg", ++ .id = SM6115_SLAVE_VENUS_THROTTLE_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node qhs_vsense_ctrl_cfg = { ++ .name = "qhs_vsense_ctrl_cfg", ++ .id = SM6115_SLAVE_VSENSE_CTRL_CFG, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node srvc_cnoc = { ++ .name = "srvc_cnoc", ++ .id = SM6115_SLAVE_SERVICE_CNOC, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static const u16 slv_snoc_bimc_nrt_links[] = { ++ SM6115_MASTER_SNOC_BIMC_NRT, ++}; ++ ++static struct qcom_icc_node slv_snoc_bimc_nrt = { ++ .name = "slv_snoc_bimc_nrt", ++ .id = SM6115_SLAVE_SNOC_BIMC_NRT, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), ++ .links = slv_snoc_bimc_nrt_links, ++}; ++ ++static const u16 slv_snoc_bimc_rt_links[] = { ++ SM6115_MASTER_SNOC_BIMC_RT, ++}; ++ ++static struct qcom_icc_node slv_snoc_bimc_rt = { ++ .name = "slv_snoc_bimc_rt", ++ .id = SM6115_SLAVE_SNOC_BIMC_RT, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), ++ .links = slv_snoc_bimc_rt_links, ++}; ++ ++static struct qcom_icc_node qhs_apss = { ++ .name = "qhs_apss", ++ .id = SM6115_SLAVE_APPSS, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static const u16 slv_snoc_cnoc_links[] = { ++ SM6115_MASTER_SNOC_CNOC ++}; ++ ++static struct qcom_icc_node slv_snoc_cnoc = { ++ .name = "slv_snoc_cnoc", ++ .id = SM6115_SLAVE_SNOC_CNOC, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 25, ++ .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), ++ .links = slv_snoc_cnoc_links, ++}; ++ ++static struct qcom_icc_node qxs_imem = { ++ .name = "qxs_imem", ++ .id = SM6115_SLAVE_OCIMEM, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 26, ++}; ++ ++static struct qcom_icc_node qxs_pimem = { ++ .name = "qxs_pimem", ++ .id = SM6115_SLAVE_PIMEM, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static const u16 slv_snoc_bimc_links[] = { ++ SM6115_MASTER_SNOC_BIMC, ++}; ++ ++static struct qcom_icc_node slv_snoc_bimc = { ++ .name = "slv_snoc_bimc", ++ .id = SM6115_SLAVE_SNOC_BIMC, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 24, ++ .num_links = ARRAY_SIZE(slv_snoc_bimc_links), ++ .links = slv_snoc_bimc_links, ++}; ++ ++static struct qcom_icc_node srvc_snoc = { ++ .name = "srvc_snoc", ++ .id = SM6115_SLAVE_SERVICE_SNOC, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static struct qcom_icc_node xs_qdss_stm = { ++ .name = "xs_qdss_stm", ++ .id = SM6115_SLAVE_QDSS_STM, ++ .channels = 1, ++ .buswidth = 4, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = 30, ++}; ++ ++static struct qcom_icc_node xs_sys_tcu_cfg = { ++ .name = "xs_sys_tcu_cfg", ++ .id = SM6115_SLAVE_TCU, ++ .channels = 1, ++ .buswidth = 8, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++}; ++ ++static const u16 slv_anoc_snoc_links[] = { ++ SM6115_MASTER_ANOC_SNOC, ++}; ++ ++static struct qcom_icc_node slv_anoc_snoc = { ++ .name = "slv_anoc_snoc", ++ .id = SM6115_SLAVE_ANOC_SNOC, ++ .channels = 1, ++ .buswidth = 16, ++ .mas_rpm_id = -1, ++ .slv_rpm_id = -1, ++ .num_links = ARRAY_SIZE(slv_anoc_snoc_links), ++ .links = slv_anoc_snoc_links, ++}; ++ ++static struct qcom_icc_node *bimc_nodes[] = { ++ [MASTER_AMPSS_M0] = &apps_proc, ++ [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, ++ [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, ++ [SNOC_BIMC_MAS] = &mas_snoc_bimc, ++ [MASTER_GRAPHICS_3D] = &qnm_gpu, ++ [MASTER_TCU_0] = &tcu_0, ++ [SLAVE_EBI_CH0] = &ebi, ++ [BIMC_SNOC_SLV] = &slv_bimc_snoc, ++}; ++ ++static const struct regmap_config bimc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x80000, ++ .fast_io = true, ++}; ++ ++static const struct qcom_icc_desc sm6115_bimc = { ++ .type = QCOM_ICC_BIMC, ++ .nodes = bimc_nodes, ++ .num_nodes = ARRAY_SIZE(bimc_nodes), ++ .regmap_cfg = &bimc_regmap_config, ++ .bus_clk_desc = &bimc_clk, ++ .keep_alive = true, ++ .qos_offset = 0x8000, ++ .ab_coeff = 153, ++}; ++ ++static struct qcom_icc_node *config_noc_nodes[] = { ++ [SNOC_CNOC_MAS] = &mas_snoc_cnoc, ++ [MASTER_QDSS_DAP] = &xm_dap, ++ [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, ++ [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, ++ [SLAVE_BIMC_CFG] = &qhs_bimc_cfg, ++ [SLAVE_BOOT_ROM] = &qhs_boot_rom, ++ [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, ++ [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, ++ [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, ++ [SLAVE_CLK_CTL] = &qhs_clk_ctl, ++ [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, ++ [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, ++ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, ++ [SLAVE_DCC_CFG] = &qhs_dcc_cfg, ++ [SLAVE_DDR_PHY_CFG] = &qhs_ddr_phy_cfg, ++ [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, ++ [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, ++ [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, ++ [SLAVE_GPU_CFG] = &qhs_gpu_cfg, ++ [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, ++ [SLAVE_HWKM_CORE] = &qhs_hwkm, ++ [SLAVE_IMEM_CFG] = &qhs_imem_cfg, ++ [SLAVE_IPA_CFG] = &qhs_ipa_cfg, ++ [SLAVE_LPASS] = &qhs_lpass, ++ [SLAVE_MAPSS] = &qhs_mapss, ++ [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, ++ [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, ++ [SLAVE_CNOC_MSS] = &qhs_mss, ++ [SLAVE_PDM] = &qhs_pdm, ++ [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, ++ [SLAVE_PKA_CORE] = &qhs_pka_wrapper, ++ [SLAVE_PMIC_ARB] = &qhs_pmic_arb, ++ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, ++ [SLAVE_QM_CFG] = &qhs_qm_cfg, ++ [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, ++ [SLAVE_QPIC] = &qhs_qpic, ++ [SLAVE_QUP_0] = &qhs_qup0, ++ [SLAVE_RPM] = &qhs_rpm, ++ [SLAVE_SDCC_1] = &qhs_sdc1, ++ [SLAVE_SDCC_2] = &qhs_sdc2, ++ [SLAVE_SECURITY] = &qhs_security, ++ [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, ++ [SLAVE_TCSR] = &qhs_tcsr, ++ [SLAVE_TLMM] = &qhs_tlmm, ++ [SLAVE_USB3] = &qhs_usb3, ++ [SLAVE_VENUS_CFG] = &qhs_venus_cfg, ++ [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, ++ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, ++ [SLAVE_SERVICE_CNOC] = &srvc_cnoc, ++}; ++ ++static const struct regmap_config cnoc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x6200, ++ .fast_io = true, ++}; ++ ++static const struct qcom_icc_desc sm6115_config_noc = { ++ .type = QCOM_ICC_QNOC, ++ .nodes = config_noc_nodes, ++ .num_nodes = ARRAY_SIZE(config_noc_nodes), ++ .regmap_cfg = &cnoc_regmap_config, ++ .intf_clocks = cnoc_intf_clocks, ++ .num_intf_clocks = ARRAY_SIZE(cnoc_intf_clocks), ++ .bus_clk_desc = &bus_1_clk, ++ .keep_alive = true, ++}; ++ ++static struct qcom_icc_node *sys_noc_nodes[] = { ++ [MASTER_CRYPTO_CORE0] = &crypto_c0, ++ [MASTER_SNOC_CFG] = &qhm_snoc_cfg, ++ [MASTER_TIC] = &qhm_tic, ++ [MASTER_ANOC_SNOC] = &mas_anoc_snoc, ++ [BIMC_SNOC_MAS] = &mas_bimc_snoc, ++ [MASTER_PIMEM] = &qxm_pimem, ++ [MASTER_QDSS_BAM] = &qhm_qdss_bam, ++ [MASTER_QPIC] = &qhm_qpic, ++ [MASTER_QUP_0] = &qhm_qup0, ++ [MASTER_IPA] = &qxm_ipa, ++ [MASTER_QDSS_ETR] = &xm_qdss_etr, ++ [MASTER_SDCC_1] = &xm_sdc1, ++ [MASTER_SDCC_2] = &xm_sdc2, ++ [MASTER_USB3] = &xm_usb3_0, ++ [SLAVE_APPSS] = &qhs_apss, ++ [SNOC_CNOC_SLV] = &slv_snoc_cnoc, ++ [SLAVE_OCIMEM] = &qxs_imem, ++ [SLAVE_PIMEM] = &qxs_pimem, ++ [SNOC_BIMC_SLV] = &slv_snoc_bimc, ++ [SLAVE_SERVICE_SNOC] = &srvc_snoc, ++ [SLAVE_QDSS_STM] = &xs_qdss_stm, ++ [SLAVE_TCU] = &xs_sys_tcu_cfg, ++ [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, ++}; ++ ++static const struct regmap_config sys_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x5f080, ++ .fast_io = true, ++}; ++ ++static const struct qcom_icc_desc sm6115_sys_noc = { ++ .type = QCOM_ICC_QNOC, ++ .nodes = sys_noc_nodes, ++ .num_nodes = ARRAY_SIZE(sys_noc_nodes), ++ .regmap_cfg = &sys_noc_regmap_config, ++ .intf_clocks = snoc_intf_clocks, ++ .num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks), ++ .bus_clk_desc = &bus_2_clk, ++ .keep_alive = true, ++}; ++ ++static struct qcom_icc_node *clk_virt_nodes[] = { ++ [MASTER_QUP_CORE_0] = &qup0_core_master, ++ [SLAVE_QUP_CORE_0] = &qup0_core_slave, ++}; ++ ++static const struct qcom_icc_desc sm6115_clk_virt = { ++ .type = QCOM_ICC_QNOC, ++ .nodes = clk_virt_nodes, ++ .num_nodes = ARRAY_SIZE(clk_virt_nodes), ++ .regmap_cfg = &sys_noc_regmap_config, ++ .bus_clk_desc = &qup_clk, ++ .keep_alive = true, ++}; ++ ++static struct qcom_icc_node *mmnrt_virt_nodes[] = { ++ [MASTER_CAMNOC_SF] = &qnm_camera_nrt, ++ [MASTER_VIDEO_P0] = &qxm_venus0, ++ [MASTER_VIDEO_PROC] = &qxm_venus_cpu, ++ [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, ++}; ++ ++static const struct qcom_icc_desc sm6115_mmnrt_virt = { ++ .type = QCOM_ICC_QNOC, ++ .nodes = mmnrt_virt_nodes, ++ .num_nodes = ARRAY_SIZE(mmnrt_virt_nodes), ++ .regmap_cfg = &sys_noc_regmap_config, ++ .bus_clk_desc = &mmaxi_0_clk, ++ .keep_alive = true, ++ .ab_coeff = 142, ++}; ++ ++static struct qcom_icc_node *mmrt_virt_nodes[] = { ++ [MASTER_CAMNOC_HF] = &qnm_camera_rt, ++ [MASTER_MDP_PORT0] = &qxm_mdp0, ++ [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, ++}; ++ ++static const struct qcom_icc_desc sm6115_mmrt_virt = { ++ .type = QCOM_ICC_QNOC, ++ .nodes = mmrt_virt_nodes, ++ .num_nodes = ARRAY_SIZE(mmrt_virt_nodes), ++ .regmap_cfg = &sys_noc_regmap_config, ++ .bus_clk_desc = &mmaxi_1_clk, ++ .keep_alive = true, ++ .ab_coeff = 139, ++}; ++ ++static const struct of_device_id qnoc_of_match[] = { ++ { .compatible = "qcom,sm6115-bimc", .data = &sm6115_bimc }, ++ { .compatible = "qcom,sm6115-clk-virt", .data = &sm6115_clk_virt }, ++ { .compatible = "qcom,sm6115-cnoc", .data = &sm6115_config_noc }, ++ { .compatible = "qcom,sm6115-mmrt-virt", .data = &sm6115_mmrt_virt }, ++ { .compatible = "qcom,sm6115-mmnrt-virt", .data = &sm6115_mmnrt_virt }, ++ { .compatible = "qcom,sm6115-snoc", .data = &sm6115_sys_noc }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qnoc_of_match); ++ ++static struct platform_driver qnoc_driver = { ++ .probe = qnoc_probe, ++ .remove = qnoc_remove, ++ .driver = { ++ .name = "qnoc-sm6115", ++ .of_match_table = qnoc_of_match, ++ .sync_state = icc_sync_state, ++ }, ++}; ++ ++static int __init qnoc_driver_init(void) ++{ ++ return platform_driver_register(&qnoc_driver); ++} ++core_initcall(qnoc_driver_init); ++ ++static void __exit qnoc_driver_exit(void) ++{ ++ platform_driver_unregister(&qnoc_driver); ++} ++module_exit(qnoc_driver_exit); ++ ++MODULE_DESCRIPTION("SM6115 NoC driver"); ++MODULE_LICENSE("GPL"); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch new file mode 100644 index 0000000..80ad1e6 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch @@ -0,0 +1,86 @@ +From ff753723bf3916770c1e2580fe1f34ad9d6f0283 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Sat, 4 Nov 2023 21:56:35 +0100 +Subject: [PATCH] arm64: dts: qcom: qrb4210-rb2: Enable MPSS and Wi-Fi + +Enable the remote processors and tighten up the regulators to enable +Wi-Fi functionality on the RB2. + +For reference, the hw/sw identifies as: + +qmi chip_id 0x150 chip_family 0x4002 board_id 0xff soc_id 0x40670000 +qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 +fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 +wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 +kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 +firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi +crc32 b3d4b790 +htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231104-topic-rb2_wifi-v1-1-fd45ae535d2f@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git ff753723bf3916770c1e2580fe1f34ad9d6f0283] +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 24 ++++++++++++++++++++---- + 1 file changed, 20 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 33c312ae842e..7c19f874fa71 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -281,6 +281,12 @@ &remoteproc_cdsp { + status = "okay"; + }; + ++&remoteproc_mpss { ++ firmware-name = "qcom/qrb4210/modem.mbn"; ++ ++ status = "okay"; ++}; ++ + &rpm_requests { + regulators { + compatible = "qcom,rpm-pm6125-regulators"; +@@ -347,8 +353,8 @@ vreg_l7a_1p256: l7 { + }; + + vreg_l8a_0p664: l8 { +- regulator-min-microvolt = <400000>; +- regulator-max-microvolt = <728000>; ++ regulator-min-microvolt = <640000>; ++ regulator-max-microvolt = <640000>; + }; + + vreg_l9a_1p8: l9 { +@@ -428,8 +434,8 @@ vreg_l22a_2p96: l22 { + }; + + vreg_l23a_3p3: l23 { +- regulator-min-microvolt = <3200000>; +- regulator-max-microvolt = <3400000>; ++ regulator-min-microvolt = <3312000>; ++ regulator-max-microvolt = <3312000>; + regulator-allow-set-load; + }; + +@@ -620,6 +626,16 @@ &usb_qmpphy { + status = "okay"; + }; + ++&wifi { ++ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; ++ vdd-1.8-xo-supply = <&vreg_l16a_1p3>; ++ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; ++ vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; ++ qcom,ath10k-calibration-variant = "Thundercomm_RB2"; ++ ++ status = "okay"; ++}; ++ + &xo_board { + clock-frequency = <19200000>; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch new file mode 100644 index 0000000..385e1b2 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch @@ -0,0 +1,66 @@ +From ba5f5610841fad3b15c69c6949ed6e19bd5b466e Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 27 Nov 2023 12:23:27 +0100 +Subject: [PATCH 1/2] arm64: dts: qcom: sm6115: Add UART3 + +Hook up UART3, usually used for communicating with a Bluetooth module. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231120-topic-rb2_bt-v2-1-4bbf266258ef@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git ba5f5610841fad3b15c69c6949ed6e19bd5b466e] +--- + arch/arm64/boot/dts/qcom/sm6115.dtsi | 30 ++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index 839c60351240..0d13d7bf6bd1 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -273,6 +273,25 @@ memory@80000000 { + reg = <0 0x80000000 0 0>; + }; + ++ qup_opp_table: opp-table-qup { ++ compatible = "operating-points-v2"; ++ ++ opp-75000000 { ++ opp-hz = /bits/ 64 <75000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ }; ++ ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ required-opps = <&rpmpd_opp_svs>; ++ }; ++ ++ opp-128000000 { ++ opp-hz = /bits/ 64 <128000000>; ++ required-opps = <&rpmpd_opp_nom>; ++ }; ++ }; ++ + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; +@@ -1208,6 +1227,17 @@ spi3: spi@4a8c000 { + status = "disabled"; + }; + ++ uart3: serial@4a8c000 { ++ compatible = "qcom,geni-uart"; ++ reg = <0x0 0x04a8c000 0x0 0x4000>; ++ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; ++ clock-names = "se"; ++ power-domains = <&rpmpd SM6115_VDDCX>; ++ operating-points-v2 = <&qup_opp_table>; ++ status = "disabled"; ++ }; ++ + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch new file mode 100644 index 0000000..a3c3832 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch @@ -0,0 +1,475 @@ +From b3eaa47395b9d0fc593e7f8b8b0abb4c769ad30d Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 11 Dec 2023 10:23:59 +0100 +Subject: [PATCH] arm64: dts: qcom: sm6115: Hook up interconnects + +Add interconnect provider nodes and hook up interconnects to consumer +devices, including bwmon. + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231209-topic-6115iccdt-v1-2-f62da62b7276@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git b3eaa47395b9d0fc593e7f8b8b0abb4c769ad30d] +--- + arch/arm64/boot/dts/qcom/sm6115.dtsi | 277 +++++++++++++++++++++++++++ + 1 file changed, 277 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index 72a833b7cd83..160e098f1075 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -10,6 +10,8 @@ + #include <dt-bindings/dma/qcom-gpi.h> + #include <dt-bindings/firmware/qcom,scm.h> + #include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/interconnect/qcom,rpm-icc.h> ++#include <dt-bindings/interconnect/qcom,sm6115.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + +@@ -264,6 +266,8 @@ firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; ++ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + }; + }; + +@@ -878,6 +882,43 @@ usb_qmpphy: phy@1615000 { + status = "disabled"; + }; + ++ system_noc: interconnect@1880000 { ++ compatible = "qcom,sm6115-snoc"; ++ reg = <0x0 0x01880000 0x0 0x5f080>; ++ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, ++ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, ++ <&rpmcc RPM_SMD_IPA_CLK>; ++ clock-names = "cpu_axi", ++ "ufs_axi", ++ "usb_axi", ++ "ipa"; ++ #interconnect-cells = <2>; ++ ++ clk_virt: interconnect-clk { ++ compatible = "qcom,sm6115-clk-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmrt_virt: interconnect-mmrt { ++ compatible = "qcom,sm6115-mmrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ ++ mmnrt_virt: interconnect-mmnrt { ++ compatible = "qcom,sm6115-mmnrt-virt"; ++ #interconnect-cells = <2>; ++ }; ++ }; ++ ++ config_noc: interconnect@1900000 { ++ compatible = "qcom,sm6115-cnoc"; ++ reg = <0x0 0x01900000 0x0 0x6200>; ++ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; ++ clock-names = "usb_axi"; ++ #interconnect-cells = <2>; ++ }; ++ + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b40000 0x0 0x7000>; +@@ -902,6 +943,60 @@ rng: rng@1b53000 { + clock-names = "core"; + }; + ++ pmu@1b8e300 { ++ compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; ++ reg = <0x0 0x01b8e300 0x0 0x600>; ++ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; ++ ++ operating-points-v2 = <&cpu_bwmon_opp_table>; ++ interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; ++ ++ cpu_bwmon_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-0 { ++ opp-peak-kBps = <(200 * 4 * 1000)>; ++ }; ++ ++ opp-1 { ++ opp-peak-kBps = <(300 * 4 * 1000)>; ++ }; ++ ++ opp-2 { ++ opp-peak-kBps = <(451 * 4 * 1000)>; ++ }; ++ ++ opp-3 { ++ opp-peak-kBps = <(547 * 4 * 1000)>; ++ }; ++ ++ opp-4 { ++ opp-peak-kBps = <(681 * 4 * 1000)>; ++ }; ++ ++ opp-5 { ++ opp-peak-kBps = <(768 * 4 * 1000)>; ++ }; ++ ++ opp-6 { ++ opp-peak-kBps = <(1017 * 4 * 1000)>; ++ }; ++ ++ opp-7 { ++ opp-peak-kBps = <(1353 * 4 * 1000)>; ++ }; ++ ++ opp-8 { ++ opp-peak-kBps = <(1555 * 4 * 1000)>; ++ }; ++ ++ opp-9 { ++ opp-peak-kBps = <(1804 * 4 * 1000)>; ++ }; ++ }; ++ }; ++ + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, +@@ -931,6 +1026,12 @@ tsens0: thermal-sensor@4411000 { + #thermal-sensor-cells = <1>; + }; + ++ bimc: interconnect@4480000 { ++ compatible = "qcom,sm6115-bimc"; ++ reg = <0x0 0x04480000 0x0 0x80000>; ++ #interconnect-cells = <2>; ++ }; ++ + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; +@@ -958,8 +1059,42 @@ sdhc_1: mmc@4744000 { + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + ++ power-domains = <&rpmpd SM6115_VDDCX>; ++ operating-points-v2 = <&sdhc1_opp_table>; ++ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; ++ + bus-width = <8>; + status = "disabled"; ++ ++ sdhc1_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <102400 65000>; ++ }; ++ ++ opp-192000000 { ++ opp-hz = /bits/ 64 <192000000>; ++ required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ required-opps = <&rpmpd_opp_svs_plus>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <204800 200000>; ++ }; ++ }; + }; + + sdhc_2: mmc@4784000 { +@@ -980,6 +1115,12 @@ sdhc_2: mmc@4784000 { + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; ++ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; ++ interconnect-names = "sdhc-ddr", ++ "cpu-sdhc"; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; +@@ -992,11 +1133,15 @@ sdhc2_opp_table: opp-table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; ++ opp-peak-kBps = <250000 133320>; ++ opp-avg-kBps = <261438 150000>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; ++ opp-peak-kBps = <800000 300000>; ++ opp-avg-kBps = <261438 300000>; + }; + }; + }; +@@ -1103,6 +1248,15 @@ i2c0: i2c@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1119,6 +1273,15 @@ spi0: spi@4a80000 { + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1135,6 +1298,12 @@ i2c1: i2c@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1151,6 +1320,15 @@ spi1: spi@4a84000 { + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1167,6 +1345,15 @@ i2c2: i2c@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1183,6 +1370,15 @@ spi2: spi@4a88000 { + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1199,6 +1395,15 @@ i2c3: i2c@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1215,6 +1420,15 @@ spi3: spi@4a8c000 { + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1228,6 +1442,12 @@ uart3: serial@4a8c000 { + clock-names = "se"; + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&qup_opp_table>; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -1242,6 +1462,15 @@ i2c4: i2c@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1258,6 +1487,15 @@ spi4: spi@4a90000 { + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1269,6 +1507,12 @@ uart4: serial@4a90000 { + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config"; + status = "disabled"; + }; + +@@ -1283,6 +1527,15 @@ i2c5: i2c@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1299,6 +1552,15 @@ spi5: spi@4a94000 { + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; ++ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG ++ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, ++ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; ++ interconnect-names = "qup-core", ++ "qup-config", ++ "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -1330,6 +1592,14 @@ usb: usb@4ef8800 { + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; ++ /* TODO: USB<->IPA path */ ++ interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; ++ interconnect-names = "usb-ddr", ++ "apps-usb"; ++ + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + +@@ -1501,6 +1771,13 @@ mdss: display-subsystem@5e00000 { + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ++ interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG ++ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, ++ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG ++ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; ++ interconnect-names = "mdp0-mem", ++ "cpu-cfg"; ++ + #address-cells = <2>; + #size-cells = <2>; + ranges; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch new file mode 100644 index 0000000..d70ef6a --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch @@ -0,0 +1,162 @@ +From cab60b166575dd6db4c85487e87a9b677e04c153 Mon Sep 17 00:00:00 2001 +From: Konrad Dybcio <konrad.dybcio@linaro.org> +Date: Mon, 27 Nov 2023 12:23:28 +0100 +Subject: [PATCH 2/2] arm64: dts: qcom: qrb4210-rb2: Enable bluetooth + +Enable the QCA bluetooth on RB2. It identifies like the following: + +Bluetooth: hci0: QCA Product ID :0x0000000a +Bluetooth: hci0: QCA SOC Version :0x40020150 +Bluetooth: hci0: QCA ROM Version :0x00000201 +Bluetooth: hci0: QCA Patch Version:0x00000001 +Bluetooth: hci0: QCA controller version 0x01500201 + +Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> +Link: https://lore.kernel.org/r/20231120-topic-rb2_bt-v2-2-4bbf266258ef@linaro.org +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git cab60b166575dd6db4c85487e87a9b677e04c153] +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 87 +++++++++++++++++++++++- + 1 file changed, 86 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 9738c0dacd58..33c312ae842e 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -15,6 +15,7 @@ / { + + aliases { + serial0 = &uart4; ++ serial1 = &uart3; + }; + + chosen { +@@ -352,7 +353,8 @@ vreg_l8a_0p664: l8 { + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2000000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { +@@ -389,11 +391,13 @@ vreg_l15a_3p128: l15 { + vreg_l16a_1p3: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; ++ regulator-allow-set-load; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; ++ regulator-allow-set-load; + }; + + vreg_l18a_1p232: l18 { +@@ -426,6 +430,7 @@ vreg_l22a_2p96: l22 { + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; ++ regulator-allow-set-load; + }; + + vreg_l24a_2p96: l24 { +@@ -487,6 +492,66 @@ &tlmm { + <56 3>, <61 2>, <64 1>, + <68 1>, <72 8>, <96 1>; + ++ uart3_default: uart3-default-state { ++ cts-pins { ++ pins = "gpio8"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-bus-hold; ++ }; ++ ++ rts-pins { ++ pins = "gpio9"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ ++ tx-pins { ++ pins = "gpio10"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ ++ rx-pins { ++ pins = "gpio11"; ++ function = "qup3"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ }; ++ ++ uart3_sleep: uart3-sleep-state { ++ cts-pins { ++ pins = "gpio8"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-bus-hold; ++ }; ++ ++ rts-pins { ++ pins = "gpio9"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-down; ++ }; ++ ++ tx-pins { ++ pins = "gpio10"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ ++ rx-pins { ++ pins = "gpio11"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-up; ++ }; ++ }; ++ + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; +@@ -508,6 +573,26 @@ sdc2_card_det_n: sd-card-det-n-state { + }; + }; + ++&uart3 { ++ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, ++ <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; ++ pinctrl-0 = <&uart3_default>; ++ pinctrl-1 = <&uart3_sleep>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "qcom,wcn3988-bt"; ++ ++ vddio-supply = <&vreg_l9a_1p8>; ++ vddxo-supply = <&vreg_l16a_1p3>; ++ vddrf-supply = <&vreg_l17a_1p3>; ++ vddch0-supply = <&vreg_l23a_3p3>; ++ enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; ++ max-speed = <3200000>; ++ }; ++}; ++ + &uart4 { + status = "okay"; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch new file mode 100644 index 0000000..15f9507 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch @@ -0,0 +1,30 @@ +From 89293aa2737299d021d42fef649bdcd191953a0b Mon Sep 17 00:00:00 2001 +From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Date: Tue, 21 Nov 2023 13:22:49 +0200 +Subject: [PATCH 2/3] arm64: dts: qcom: qrb4210-rb2: Select USB3 host mode by + default + +The USB3 controller mode is selected by on-board DIP switches, and +by default it is set to the host mode, specify the selection. + +Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 7c19f874fa71..97344508c94f 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -609,6 +609,7 @@ &usb { + + &usb_dwc3 { + maximum-speed = "super-speed"; ++ dr_mode = "host"; + }; + + &usb_hsphy { +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch new file mode 100644 index 0000000..fd344bc --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch @@ -0,0 +1,53 @@ +From 3d1bd03aa758d8766f3d7e3cae8aa24d9fe0bf09 Mon Sep 17 00:00:00 2001 +From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Date: Tue, 21 Nov 2023 13:20:18 +0200 +Subject: [PATCH 3/3] arm64: dts: qcom: sm6115: Enable USB3 SS phy + +There is no reason to limit USB3 controller to USB2 functionality, +moreover it fixes a contradiction with the selected super-speed +mode on RB2 board. Additionally specify the OTG function in the SoC +specific description. + +Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 - + arch/arm64/boot/dts/qcom/sm6115.dtsi | 3 ++- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +index 97344508c94f..549f36276269 100644 +--- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts ++++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +@@ -608,7 +608,6 @@ &usb { + }; + + &usb_dwc3 { +- maximum-speed = "super-speed"; + dr_mode = "host"; + }; + +diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi +index ca49e8c7f6e6..3680dc203263 100644 +--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi +@@ -1607,7 +1607,6 @@ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + interconnect-names = "usb-ddr", + "apps-usb"; + +- qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_dwc3: usb@4e00000 { +@@ -1622,6 +1621,8 @@ usb_dwc3: usb@4e00000 { + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; ++ maximum-speed = "super-speed"; ++ dr_mode = "otg"; + }; + }; + +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcm6490-Remove-voltage-voting-for-.patch b/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcm6490-Remove-voltage-voting-for-.patch new file mode 100644 index 0000000..7338353 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcm6490-Remove-voltage-voting-for-.patch @@ -0,0 +1,54 @@ +From 5d52be9a7c56e416fe98744f025e8b4aa92fd849 Mon Sep 17 00:00:00 2001 +From: Umang Chheda <quic_uchheda@quicinc.com> +Date: Wed, 11 Oct 2023 20:57:16 +0530 +Subject: [PATCH 1/2] PENDING: arm64: dts: qcm6490: remove voltage voting for + USB rails for idp + +USB driver does not vote for voltage on hsphy and ssphy +rails. Due to which the initial voltage set by bootloader +is overridden by regulator framework with min voltage specified +on regulator registration. + +Fix this temporarily by removing voltage voting support, which +will prevent regulator framework overriding the voltage set by +bootloader. + +This commit will be reverted once voltage voting support is added +in USB driver. + +Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 14c73f55ea52..89e653c93ae8 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -519,6 +519,20 @@ &vreg_l9b_1p2 { + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; + }; + ++&vreg_l1b_0p912 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ ++&vreg_l10c_0p88 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ + &wifi { + memory-region = <&wlan_fw_mem>; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch b/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch new file mode 100644 index 0000000..a2359f6 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/workarounds/0001-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch @@ -0,0 +1,49 @@ +From 328f42bd030f43574f516906fa0f25fcc5f19c30 Mon Sep 17 00:00:00 2001 +From: Umang Chheda <quic_uchheda@quicinc.com> +Date: Wed, 11 Oct 2023 20:32:47 +0530 +Subject: [PATCH 1/2] PENDING: arm64: dts: qcom: Remove voltage vote support + for UFS for IDP + +UFS rails have different voltage requirement for UFS2.x v/s UFS3.x. +Bootloader sets the proper voltage based on UFS type. There can be +case where the voltage set by bootloader is overridden by HLOS client. + +To prevent above issue, Add change to remove voltage voting support +for UFS rails. + +Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 7f682093e954..5b96b77db0c2 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -505,6 +505,20 @@ &usb_1_qmpphy { + status = "okay"; + }; + ++&vreg_l7b_2p952 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ ++&vreg_l9b_1p2 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ + &wifi { + memory-region = <&wlan_fw_mem>; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/workarounds/0001-QCLINUX-arm64-dts-qcom-qcm6490-disable-sdhc1-for-ufs.patch b/recipes-kernel/linux/linux-yocto/workarounds/0001-QCLINUX-arm64-dts-qcom-qcm6490-disable-sdhc1-for-ufs.patch new file mode 100644 index 0000000..feb48b5 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/workarounds/0001-QCLINUX-arm64-dts-qcom-qcm6490-disable-sdhc1-for-ufs.patch @@ -0,0 +1,34 @@ +From d968bbe73d04fc76db30bdefc9b00fb4128d6b4e Mon Sep 17 00:00:00 2001 +From: Manish Pandey <quic_mapa@quicinc.com> +Date: Fri, 13 Oct 2023 19:38:59 +0530 +Subject: [PATCH] QCLINUX: arm64: dts: qcom: qcm6490: disable sdhc1 for ufs + target + +Disable sdhc1 for QCM6490 for ufs boot target to avoid probe +for sdhc1 as vreg_l7b_2p9 is shared regulator for both ufs vcc +and emmc vcc. Currently this is causing probe failure for ufs. + +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +index 424cd9c2b092..7f682093e954 100644 +--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts ++++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +@@ -450,7 +450,7 @@ &sdhc_1 { + vmmc-supply = <&vreg_l7b_2p952>; + vqmmc-supply = <&vreg_l19b_1p8>; + +- status = "okay"; ++ status = "disabled"; + }; + + &tlmm { +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch b/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch new file mode 100644 index 0000000..9b569b3 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch @@ -0,0 +1,48 @@ +From c0027585783c96a1ba37e8ea604af4c7c73e8154 Mon Sep 17 00:00:00 2001 +From: Umang Chheda <quic_uchheda@quicinc.com> +Date: Wed, 18 Oct 2023 18:12:00 +0530 +Subject: [PATCH 2/2] PENDING: arm64: dts: qcom: Remove voltage vote support + for UFS for RB3 + +UFS rails have different voltage requirement for UFS2.x v/s UFS3.x. +Bootloader sets the proper voltage based on UFS type. There can be +case where the voltage set by bootloader is overridden by HLOS client. + +To prevent above issue, Add change to remove voltage voting support +for UFS rails for QC6490 RB3 platform. + +Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index 6dbeb182d014..f13ab20906f8 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -488,6 +488,20 @@ &usb_1_qmpphy { + status = "okay"; + }; + ++&vreg_l7b_2p952 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ ++&vreg_l9b_1p2 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ + &wifi { + memory-region = <&wlan_fw_mem>; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcs6490-rb3-Remove-voltage-voting-.patch b/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcs6490-rb3-Remove-voltage-voting-.patch new file mode 100644 index 0000000..9c0ddcd --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/workarounds/0002-PENDING-arm64-dts-qcs6490-rb3-Remove-voltage-voting-.patch @@ -0,0 +1,60 @@ +From b9b8286e4a3d72353ee90181f10507e2dfb1fd2b Mon Sep 17 00:00:00 2001 +From: Umang Chheda <quic_uchheda@quicinc.com> +Date: Wed, 18 Oct 2023 18:14:15 +0530 +Subject: [PATCH 2/2] PENDING: arm64: dts: qcs6490-rb3: Remove voltage voting + for USB rails + +USB driver does not vote for voltage on hsphy and ssphy +rails. Due to which the initial voltage set by bootloader +is overridden by regulator framework with min voltage specified +on regulator registration. + +Fix this temporarily by removing voltage voting support, which +will prevent regulator framework overriding the voltage set by +bootloader for QCS6490 RB3 Platform. + +This commit will be reverted once voltage voting support is added +in USB driver. + +Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Pending +--- + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +index 2b30e8900991..1e20395d07ae 100644 +--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts ++++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +@@ -488,6 +488,13 @@ &usb_1_qmpphy { + status = "okay"; + }; + ++&vreg_l1b_0p912 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ + &vreg_l7b_2p952 { + /delete-property/regulator-min-microvolt; + /delete-property/regulator-max-microvolt; +@@ -502,6 +509,13 @@ &vreg_l9b_1p2 { + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; + }; + ++&vreg_l10c_0p88 { ++ /delete-property/regulator-min-microvolt; ++ /delete-property/regulator-max-microvolt; ++ regulator-allow-set-load; ++ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>; ++}; ++ + &wifi { + memory-region = <&wlan_fw_mem>; + }; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-yocto_%.bbappend b/recipes-kernel/linux/linux-yocto_%.bbappend new file mode 100644 index 0000000..8b4dc40 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto_%.bbappend @@ -0,0 +1,14 @@ +# do not override KBRANCH and SRCREV_machine, use default ones. +COMPATIBLE_MACHINE:qcom = "qcom-armv8a|qcom-armv7a" + +FILESEXTRAPATHS:prepend:qcom := "${THISDIR}/${PN}:" + +# include all Qualcomm-specific files +SRC_URI:append:qcom = " \ + file://qcom.scc \ +" + +# For boot.img +QCOM_BOOTIMG = "" +QCOM_BOOTIMG:qcom = "linux-qcom-bootimg" +inherit ${QCOM_BOOTIMG} diff --git a/recipes-kernel/linux/linux-yocto_6.6.bbappend b/recipes-kernel/linux/linux-yocto_6.6.bbappend new file mode 100644 index 0000000..eeb337c --- /dev/null +++ b/recipes-kernel/linux/linux-yocto_6.6.bbappend @@ -0,0 +1,76 @@ + +SRC_URI:append:qcom = " \ + file://0001-arm64-dts-qcom-qcm2290-temporarily-disable-cluster-i.patch \ + file://qca6390-driver/0001-dt-bindings-mfd-qcom-qca639x-add-binding-for-QCA639x.patch \ + file://qca6390-driver/0002-mfd-qca639x-add-support-for-QCA639x-powerup-sequence.patch \ + file://qca6390-driver/0003-mfd-qcom-qca639x-switch-to-platform-config-data.patch \ + file://qca6390-driver/0004-mfd-qcom-qca639x-change-qca639x-to-use-gpios-rather-.patch \ + file://qca6390-driver/0005-mfd-qcom-qca639x-Add-support-for-WCN6855.patch \ + file://qca6390-dts/0001-arm64-dts-qcom-qrb5165-rb5-add-qca639x-power-domain.patch \ + file://qca6390-dts/0002-arm64-dts-qcom-Add-Bluetooth-support-on-RB5.patch \ + file://qca6390-dts/0003-arm64-dtb-qcom-qrb5165-rb5-add-power-domain-to-pcie0.patch \ + file://generic-drivers/mpm/0001-dt-bindings-interrupt-controller-mpm-Pass-MSG-RAM-sl.patch \ + file://generic-drivers/mpm/0002-irqchip-irq-qcom-mpm-Support-passing-a-slice-of-SRAM.patch \ + file://generic-drivers/mdss-icc/0002_dt_bindings_display_msm_add_reg_bus_and_rotator_interconnects.patch \ + file://generic-drivers/mdss-icc/0001_drm_msm_mdss_switch_mdss_to_use_devm_of_icc_get.patch \ + file://generic-drivers/mdss-icc/0002_drm_msm_mdss_rename_path_references_to_mdp_path.patch \ + file://generic-drivers/mdss-icc/0003_drm_msm_mdss_inline_msm_mdss_icc_request_bw.patch \ + file://generic-drivers/mdss-icc/0004_drm_msm_mdss_handle_the_reg_bus_icc_path.patch \ + file://generic-drivers/icc/0001-interconnect-qcom-icc-rpm-Add-AB-IB-calculations-coe.patch \ + file://generic-drivers/icc/0002-interconnect-qcom-icc-rpm-Separate-out-clock-rate-ca.patch \ + file://generic-drivers/icc/0003-interconnect-qcom-icc-rpm-Let-nodes-drive-their-own-.patch \ + file://generic-drivers/icc/0004-interconnect-qcom-icc-rpm-Check-for-node-specific-ra.patch \ + file://generic-drivers/icc/0005-interconnect-qcom-qcm2290-Hook-up-MAS_APPS_PROC-s-bu.patch \ + file://generic-drivers/icc/0006-interconnect-qcom-qcm2290-Set-AB-coefficients.patch \ + file://generic-drivers/icc/0007-interconnect-qcom-qcm2290-Update-EBI-channel-configu.patch \ + file://generic-drivers/icc/0008-interconnect-qcom-sdm660-Set-AB-IB-coefficients.patch \ + file://generic-drivers/icc/0009-interconnect-qcom-msm8996-Set-AB-IB-coefficients.patch \ + file://qrb2210-drivers/0001_dt_bindings_display_msm_qcm2290_mdss_use_the_non_deprecated_dsi_compat.patch \ + file://qrb2210-drivers/0003_dt_bindings_interconnect_qcom_msm8998_bwmon_add_qcm2290_bwmon_instance.patch \ + file://qrb2210-drivers/0004_dt_bindings_firmware_qcom_scm_allow_interconnect_for_everyone.patch \ + file://qrb2210-drivers/0005_iommu_arm_smmu_qcom_add_qcm2290_mdss_compatible.patch \ + file://qrb2210-dts/sans-icc/0003_arm64_dts_qcom_qrb2210_rb1_enable_remote_processors.patch \ + file://qrb2210-dts/sans-icc/0004_arm64_dts_qcom_qrb2210_rb1_add_gpio_leds.patch \ + file://qrb2210-dts/sans-icc/0005_arm64_dts_qcom_qrb2210_rb1_hook_up_usb3.patch \ + file://qrb2210-dts/sans-icc/0001-arm64-dts-qcom-qrb2210-rb1-use-USB-host-mode.patch \ + file://qrb2210-dts/features/0006_arm64_dts_qcom_sc7180_add_the_missing_mdss_icc_path.patch \ + file://qrb2210-dts/features/0007_arm64_dts_qcom_sc7280_add_the_missing_mdss_icc_path.patch \ + file://qrb2210-dts/features/0008_arm64_dts_qcom_qcm2290_add_display_nodes.patch \ + file://qrb2210-dts/features/0009_arm64_dts_qcom_qcm2290_hook_up_interconnects.patch \ + file://qrb2210-dts/features/0010_arm64_dts_qcom_qrb2210_rb1_set_up_hdmi.patch \ + file://qrb2210-dts/features/0011_arm64_dts_qcom_qrb2210_rb1_enable_can_bus_controller.patch \ + file://qrb2210-dts/features/0012_arm64_dts_qcom_qrb2210_rb1_add_wifi_variant_property.patch \ + file://qrb2210-dts/0001-arm64-dts-qcom-qcm2290-Hook-up-MPM.patch \ + file://qrb4210-drivers/icc/0001-dt-bindings-interconnect-Add-Qualcomm-SM6115-NoC.patch \ + file://qrb4210-drivers/icc/0002-interconnect-qcom-Add-SM6115-interconnect-provider-d.patch \ + file://qrb4210-drivers/icc/0001-iommu-arm-smmu-qcom-Add-SM6115-MDSS-compatible.patch \ + file://qrb4210-dts/0001-arm64-dts-qcom-sm6115-Add-UART3.patch \ + file://qrb4210-dts/0002-arm64-dts-qcom-qrb4210-rb2-Enable-bluetooth.patch \ + file://qrb4210-dts/0001-arm64-dts-qcom-sm6115-Hook-up-interconnects.patch \ + file://qrb4210-dts/0001-arm64-dts-qcom-qrb4210-rb2-Enable-MPSS-and-Wi-Fi.patch \ + file://qrb4210-dts/usb/0002-arm64-dts-qcom-qrb4210-rb2-Select-USB3-host-mode-by-.patch \ + file://qrb4210-dts/usb/0003-arm64-dts-qcom-sm6115-Enable-USB3-SS-phy.patch \ + file://generic-drivers/0001-FROMLIST-dma-heap-Add-proper-kref-handling-on-dma-bu.patch \ + file://generic-drivers/0002-FROMLIST-dma-heap-Provide-accessors-so-that-in-kerne.patch \ + file://qcm6490-drivers/0001-FROMGIT-phy-qcom-qmp-ufs-Add-Phy-Configuration-suppo.patch \ + file://qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch \ + file://qcm6490-dtsi/0001-PENDING-arm64-dts-qcom-sc7280-Add-interconnect-paths.patch \ + file://qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-sc7280-Move-video-firmware-t.patch \ + file://qcm6490-dtsi/0001-UPSTREAM-arm64-dts-qcom-Use-QCOM_SCM_VMID-defines-fo.patch \ + file://qcm6490-board-dts/0001-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-Fairphone-.patch \ + file://qcm6490-board-dts/0002-UPSTREAM-dt-bindings-arm-qcom-Add-QCM6490-IDP-and-QC.patch \ + file://qcm6490-board-dts/0003-UPSTREAM-arm64-dts-qcom-Add-base-qcm6490-id.patch \ + file://qcm6490-board-dts/0004-UPSTREAM-arm64-dts-qcom-Add-base-qcs6490-rb3gen2-boa.patch \ + file://qcm6490-board-dts/0001-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Correct-the-.patch \ + file://qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcm6490-idp-Correct-the-volt.patch \ + file://qcm6490-board-dts/0001-FROMLIST-arm64-dts-qcom-qcm6490-idp-Update-protected.patch \ + file://qcm6490-board-dts/0002-UPSTREAM-arm64-dts-qcom-qcs6490-rb3gen2-Declare-GCC-.patch \ + file://qcm6490-board-dts/0003-BACKPORT-FROMLIST-arm64-dts-qcom-qcs6490-rb3gen2-Upd.patch \ + file://qcm6490-board-dts/0001-PENDING-arm64-dts-qcom-qcm6490-Add-UFS-nodes-for-IDP.patch \ + file://qcm6490-board-dts/0002-PENDING-arm64-dts-qcom-Add-UFS-nodes-for-qcs6490-rb3.patch \ + file://workarounds/0001-QCLINUX-arm64-dts-qcom-qcm6490-disable-sdhc1-for-ufs.patch \ + file://workarounds/0001-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch \ + file://workarounds/0002-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch \ + file://workarounds/0001-PENDING-arm64-dts-qcm6490-Remove-voltage-voting-for-.patch \ + file://workarounds/0002-PENDING-arm64-dts-qcs6490-rb3-Remove-voltage-voting-.patch \ +" diff --git a/recipes-kernel/packagegroups/packagegroup-qcom-boot.bb b/recipes-kernel/packagegroups/packagegroup-qcom-boot.bb new file mode 100644 index 0000000..4e79bf6 --- /dev/null +++ b/recipes-kernel/packagegroups/packagegroup-qcom-boot.bb @@ -0,0 +1,13 @@ +SUMMARY = "Qualcomm boot requirements" +DESCRIPTION = "A set of packages required to find the rootfs on the generic Qualcomm board" + +inherit packagegroup + +# Recommend the packages as some of them might end up being built-in +# qcom-pon is not strictly required, but it would be good to handle events if something goes wrong +RRECOMMENDS:${PN} = " \ + kernel-module-phy-qcom-qmp \ + kernel-module-qcom-pon \ + kernel-module-qnoc-sm8250 \ + kernel-module-ufs-qcom \ +" |