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Diffstat (limited to 'recipes-kernel/linux/linux-linaro-qcomlt-5.7/0001-arm64-dts-qcom-sm8250-Add-USB-and-PHY-device-nodes.patch')
-rw-r--r--recipes-kernel/linux/linux-linaro-qcomlt-5.7/0001-arm64-dts-qcom-sm8250-Add-USB-and-PHY-device-nodes.patch207
1 files changed, 0 insertions, 207 deletions
diff --git a/recipes-kernel/linux/linux-linaro-qcomlt-5.7/0001-arm64-dts-qcom-sm8250-Add-USB-and-PHY-device-nodes.patch b/recipes-kernel/linux/linux-linaro-qcomlt-5.7/0001-arm64-dts-qcom-sm8250-Add-USB-and-PHY-device-nodes.patch
deleted file mode 100644
index 2975a2a..0000000
--- a/recipes-kernel/linux/linux-linaro-qcomlt-5.7/0001-arm64-dts-qcom-sm8250-Add-USB-and-PHY-device-nodes.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From e4a349e3fce09e441f6568ca318be66709386514 Mon Sep 17 00:00:00 2001
-From: Jonathan Marek <jonathan@marek.ca>
-Date: Tue, 9 Jun 2020 15:40:24 -0400
-Subject: [PATCH] arm64: dts: qcom: sm8250: Add USB and PHY device nodes
-
-Add device nodes for the USB3 controller, QMP SS PHY and
-SNPS HS PHY.
-
-Signed-off-by: Jonathan Marek <jonathan@marek.ca>
----
- arch/arm64/boot/dts/qcom/sm8250.dtsi | 180 +++++++++++++++++++++++++++
- 1 file changed, 180 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
-index cc6c65883d88..68f9a3ce9760 100644
---- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
-@@ -1097,6 +1097,186 @@ intc: interrupt-controller@17a00000 {
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ usb_1_hsphy: phy@88e3000 {
-+ compatible = "qcom,sm8250-usb-hs-phy",
-+ "qcom,usb-snps-hs-7nm-phy";
-+ reg = <0 0x088e3000 0 0x400>;
-+ status = "disabled";
-+ #phy-cells = <0>;
-+
-+ clocks = <&rpmhcc RPMH_CXO_CLK>;
-+ clock-names = "ref";
-+
-+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
-+ };
-+
-+ usb_2_hsphy: phy@88e4000 {
-+ compatible = "qcom,sm8250-usb-hs-phy",
-+ "qcom,usb-snps-hs-7nm-phy";
-+ reg = <0 0x088e4000 0 0x400>;
-+ status = "disabled";
-+ #phy-cells = <0>;
-+
-+ clocks = <&rpmhcc RPMH_CXO_CLK>;
-+ clock-names = "ref";
-+
-+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
-+ };
-+
-+ usb_1_qmpphy: phy@88e9000 {
-+ compatible = "qcom,sm8250-qmp-usb3-phy";
-+ reg = <0 0x088e9000 0 0x200>,
-+ <0 0x088e8000 0 0x20>;
-+ reg-names = "reg-base", "dp_com";
-+ status = "disabled";
-+ #clock-cells = <1>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
-+ <&rpmhcc RPMH_CXO_CLK>,
-+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
-+ clock-names = "aux", "ref_clk_src", "com_aux";
-+
-+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
-+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
-+ reset-names = "phy", "common";
-+
-+ usb_1_ssphy: lanes@88e9200 {
-+ reg = <0 0x088e9200 0 0x200>,
-+ <0 0x088e9400 0 0x200>,
-+ <0 0x088e9c00 0 0x400>,
-+ <0 0x088e9600 0 0x200>,
-+ <0 0x088e9800 0 0x200>,
-+ <0 0x088e9a00 0 0x100>;
-+ #phy-cells = <0>;
-+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "usb3_phy_pipe_clk_src";
-+ };
-+ };
-+
-+ usb_2_qmpphy: phy@88eb000 {
-+ compatible = "qcom,sm8250-qmp-usb3-uni-phy";
-+ reg = <0 0x088eb000 0 0x200>;
-+ status = "disabled";
-+ #clock-cells = <1>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
-+ <&rpmhcc RPMH_CXO_CLK>,
-+ <&gcc GCC_USB3_SEC_CLKREF_EN>,
-+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
-+ clock-names = "aux", "ref_clk_src", "ref", "com_aux";
-+
-+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
-+ <&gcc GCC_USB3_PHY_SEC_BCR>;
-+ reset-names = "phy", "common";
-+
-+ usb_2_ssphy: lane@88eb200 {
-+ reg = <0 0x088eb200 0 0x200>,
-+ <0 0x088eb400 0 0x200>,
-+ <0 0x088eb800 0 0x800>;
-+ #phy-cells = <0>;
-+ clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
-+ };
-+ };
-+
-+ usb_1: usb@a6f8800 {
-+ compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
-+ reg = <0 0x0a6f8800 0 0x400>;
-+ status = "disabled";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ dma-ranges;
-+
-+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
-+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
-+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
-+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
-+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
-+ <&gcc GCC_USB3_SEC_CLKREF_EN>;
-+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
-+ "sleep", "xo";
-+
-+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
-+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
-+ assigned-clock-rates = <19200000>, <200000000>;
-+
-+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
-+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-+ "dm_hs_phy_irq", "ss_phy_irq";
-+
-+ power-domains = <&gcc USB30_PRIM_GDSC>;
-+
-+ resets = <&gcc GCC_USB30_PRIM_BCR>;
-+
-+ usb_1_dwc3: dwc3@a600000 {
-+ compatible = "snps,dwc3";
-+ reg = <0 0x0a600000 0 0xcd00>;
-+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
-+ //iommus = <&apps_smmu 0x0 0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_enblslpm_quirk;
-+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ };
-+ };
-+
-+ usb_2: usb@a8f8800 {
-+ compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
-+ reg = <0 0x0a8f8800 0 0x400>;
-+ status = "disabled";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ dma-ranges;
-+
-+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
-+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
-+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
-+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
-+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
-+ <&gcc GCC_USB3_SEC_CLKREF_EN>;
-+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
-+ "sleep", "xo";
-+
-+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
-+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
-+ assigned-clock-rates = <19200000>, <200000000>;
-+
-+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
-+ <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
-+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-+ "dm_hs_phy_irq", "ss_phy_irq";
-+
-+ power-domains = <&gcc USB30_SEC_GDSC>;
-+
-+ resets = <&gcc GCC_USB30_SEC_BCR>;
-+
-+ usb_2_dwc3: dwc3@a800000 {
-+ compatible = "snps,dwc3";
-+ reg = <0 0x0a800000 0 0xcd00>;
-+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+ //iommus = <&apps_smmu 0x20 0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_enblslpm_quirk;
-+ phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ };
-+ };
-+
- pdc: interrupt-controller@b220000 {
- compatible = "qcom,sm8250-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
---
-2.27.0
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-26 17:11:06 +0000