aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto_3.19.bbappend
AgeCommit message (Collapse)AuthorFilesLines
2016-02-12linux-yocto: update SRCREVs to latest stablefidoCalifornia Sullivan1-4/+4
This also includes the fix to keyring leak CVE-2016-0728. Signed-off-by: California Sullivan <california.l.sullivan@intel.com> Signed-off-by: Saul Wold <sgw@linux.intel.com>
2015-06-12linux-yocto_3.19: Update SRCREV to include driver update3.1-fido-1.8Chang Rebecca Swee Fun1-4/+4
Update SRCREV for linux-yocto-3.19 to include the following commits: e152349 drm/i915: Reset CSB read pointer in ring init a87a6ff drm/i915/bdw: Enable execlists by default where supported 6c21811 fs: aufs: fix a build error for archs which doesn't support MUTEX_SPIN_ f7e6e36 fs: yaffs2: kill f_dentry uses 2a5e3b1 intel_idle: Add support for the Airmont Core in the Cherrytrail and Bra 28c0578 intel_idle: Update support for Silvermont Core in Baytrail SOC 77bec57 intel_idle: Add ->enter_freeze callbacks ae682f3 intel_idle: support additional Broadwell model 3c88608 PM / sleep: Make it possible to quiesce timers during suspend-to-idle cd240b6 PM / sleep: Re-implement suspend-to-idle handling d3c0b95 drm/i915: New offset for reading frequencies on CHV. dac6bab drm/i915/chv: Populate total EU count on Cherryview a3f6f39 arm64: psci: move psci firmware calls out of line 374b5d0 drm/i915: Only wait for required lanes in vlv_wait_port_ready() fca99e8 Revert "drm/i915: Hack to tie both common lanes together on chv" 00682f3 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV 654b1a4 drm/i915: Implement chv display PHY lane stagger setup Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> Signed-off-by: Saul Wold <sgw@linux.intel.com>
2015-05-11linux-yocto_3.19: Update to the Intel i915 driverSaul Wold1-2/+2
0befa35 drm/i915/chv: Remove DPIO force latency causing interpair skew issue 184e037 drm/i915: Fix chv cdclk support e2a99b9 drm/i915: Increase the range of sideband address. 9d5d55e drm/i915: Disable DDR DVFS on CHV 96cce94 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV b5005319 drm/i915: Program PFI credits for VLV c7aa33e drm/i915: Rewrite VLV/CHV watermark code a421d8b drm/i915: Make sure PND deadline mode is enabled on VLV/CHV 631afc9 drm/i915: Read out display FIFO size on VLV/CHV e0dcdc0 drm/i915: Pass plane to vlv_compute_drain_latency() a6a5562 drm/i915: Reorganize VLV DDL setup bb662a4 drm/i915: Hide VLV DDL precision handling 3d2d932 drm/i915: Simplify VLV drain latency computation f686147 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines 86c658c drm/i915: Reduce CHV DDL multiplier to 16/8 8c4cdd9 drm/i915: Allow pixel clock up to 95% of cdclk on CHV d9d4fb8 drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz Signed-off-by: Saul Wold <sgw@linux.intel.com>
2015-05-07linux-yocto: Update linux-yocto v3.19.2 SRCREV to v3.19.5Ng Wei Tee1-6/+6
Use the latest HEADs of the git branches from the linux-yocto v3.19 kernel repository. Signed-off-by: Ng Wei Tee <wei.tee.ng@intel.com> [sgw - tweaked summary commit info] Signed-off-by: Saul Wold <sgw@linux.intel.com>
2015-04-15linux-yocto: Add initial support for BraswellSaul Wold1-2/+2
This meta SRCREV update adds support for the initial support for the Braswell SOC to the core BSPs. This enables CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT for the graphics driver. Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2015-04-15linux-yocto: Update BSP to latest meta and branch SRCREVSaul Wold1-6/+6
Do the SRCREV update to the latest versions of linux-yocto to match the fido release, this removes warnings that where noted during the first round of 3.19. Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2015-02-20linux-yocto-3.19: Add 3.19 bbappend for the Intel common BSPsDarren Hart1-0/+28
Add the 3.19 bbappend for the Intel common BSPs. Signed-off-by: Darren Hart <dvhart@linux.intel.com>