From xxxx Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 18 Apr 2014 10:11:00 +0100 Subject: [PATCH 06/21] core Quark patch --- arch/x86/Kconfig | 25 +- arch/x86/include/asm/imr.h | 22 + arch/x86/include/asm/qrk.h | 78 + arch/x86/include/asm/serial.h | 6 + arch/x86/kernel/cpu/intel.c | 11 + arch/x86/kernel/setup.c | 5 +- arch/x86/platform/efi/efi-bgrt.c | 20 +- include/linux/efi-bgrt.h | 2 + meta/cfg/kernel-cache/bsp/quark/quark.cfg | 3063 +++++++++++++++++++++++++++++ 9 files changed, 3225 insertions(+), 7 deletions(-) create mode 100644 arch/x86/include/asm/imr.h create mode 100644 arch/x86/include/asm/qrk.h create mode 100644 meta/cfg/kernel-cache/bsp/quark/quark.cfg diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0694d09..a10027f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -417,6 +417,15 @@ config X86_INTEL_CE This option compiles in support for the CE4100 SOC for settop boxes and media devices. +config INTEL_QUARK_X1000_SOC + bool "Intel Quark X1000 SOC support" + depends on M586TSC + select ARCH_REQUIRE_GPIOLIB + select I2C + ---help--- + Quark X1000 SOC support . This option enables probing for various + PCI-IDs of several on-chip devices provided by the X1000 + config X86_WANT_INTEL_MID bool "Intel MID platform support" depends on X86_32 @@ -500,6 +509,13 @@ config X86_SUPPORTS_MEMORY_FAILURE depends on X86_64 || !SPARSEMEM select ARCH_SUPPORTS_MEMORY_FAILURE +menu "Intel Media SOC Gen3 support" + +config ARCH_GEN3 + bool "Enable Intel Media SOC Gen3 support" + default y + +endmenu config X86_VISWS bool "SGI 320/540 (Visual Workstation)" depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT @@ -1169,7 +1185,7 @@ config ARCH_PHYS_ADDR_T_64BIT config ARCH_DMA_ADDR_T_64BIT def_bool y - depends on X86_64 || HIGHMEM64G + depends on X86_64 || HIGHMEM64G && !INTEL_QUARK_X1000_SOC config DIRECT_GBPAGES bool "Enable 1GB pages for kernel pagetables" if EXPERT @@ -1524,6 +1540,13 @@ config EFI_STUB See Documentation/x86/efi-stub.txt for more information. +config EFI_CAPSULE + tristate "EFI capsule update support" + depends on EFI + ---help--- + This kernel feature allows for loading of EFI capsule code + with callbacks into the EDK firmware to execute update + config SECCOMP def_bool y prompt "Enable seccomp to safely compute untrusted bytecode" diff --git a/arch/x86/include/asm/imr.h b/arch/x86/include/asm/imr.h new file mode 100644 index 0000000..876d499 --- /dev/null +++ b/arch/x86/include/asm/imr.h @@ -0,0 +1,22 @@ +/* + * imr.h: Intel Quark platform imr setup code + * + * (C) Copyright 2012 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ +#ifndef _ASM_X86_IMR_H +#define _ASM_X86_IMR_H + +#if defined(CONFIG_INTEL_QUARK_X1000_SOC) + extern int intel_qrk_imr_runt_setparams(void); + extern int intel_qrk_imr_lockall(void); +#else + static void intel_qrk_imr_runt_setparams(void){} + static void intel_qrk_imr_lockall(void){} +#endif + +#endif /* _ASM_X86_IMR_H */ diff --git a/arch/x86/include/asm/qrk.h b/arch/x86/include/asm/qrk.h new file mode 100644 index 0000000..ed4dab4 --- /dev/null +++ b/arch/x86/include/asm/qrk.h @@ -0,0 +1,78 @@ +/* + * Copyright(c) 2013 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _ASM_X86_QRK_H +#define _ASM_X86_QRK_H + +#include +#include + +/** + * qrk_pci_pvm_mask + * + * Mask PVM bit on a per function basis. Quark SC components have but one + * vector each - so we mask for what we need + */ +static inline void qrk_pci_pvm_mask(struct pci_dev * dev) +{ + struct msi_desc *entry; + int mask_bits = 1; + + if(unlikely(dev->msi_enabled == 0)) + return; + + entry = list_first_entry(&dev->msi_list, struct msi_desc, list); + + if(unlikely(entry == NULL)) + return; + + pci_write_config_dword(dev, entry->mask_pos, mask_bits); +} + +/** + * qrk_pci_pvm_mask + * + * UnMask PVM bit on a per function basis. Quark SC components have but one + * vector each - so we unmask for what we need + */ +static inline void qrk_pci_pvm_unmask(struct pci_dev * dev) +{ + struct msi_desc *entry; + int mask_bits = 0; + + if(unlikely(dev->msi_enabled == 0)) + return; + + entry = list_first_entry(&dev->msi_list, struct msi_desc, list); + + if(unlikely(entry == NULL)) + return; + + pci_write_config_dword(dev, entry->mask_pos, mask_bits); +} + +/* Convienence macros */ +#if defined(CONFIG_INTEL_QUARK_X1000_SOC) + #define mask_pvm(x) qrk_pci_pvm_mask(x) + #define unmask_pvm(x) qrk_pci_pvm_unmask(x) +#else + #define mask_pvm(x) + #define unmask_pvm(x) +#endif + +/* Serial */ +#if defined(CONFIG_INTEL_QUARK_X1000_SOC) + #define SERIAL_PORT_DFNS + #define BASE_BAUD 2764800 +#endif + +#endif /* _ASM_X86_QRK_H */ diff --git a/arch/x86/include/asm/serial.h b/arch/x86/include/asm/serial.h index 628c801..9bcaf85 100644 --- a/arch/x86/include/asm/serial.h +++ b/arch/x86/include/asm/serial.h @@ -1,6 +1,8 @@ #ifndef _ASM_X86_SERIAL_H #define _ASM_X86_SERIAL_H +#include + /* * This assumes you have a 1.8432 MHz clock for your UART. * @@ -8,7 +10,9 @@ * clock, since the 16550A is capable of handling a top speed of 1.5 * megabits/second; but this requires the faster clock. */ +#ifndef BASE_BAUD #define BASE_BAUD ( 1843200 / 16 ) +#endif /* Standard COM flags (except for COM4, because of the 8514 problem) */ #ifdef CONFIG_SERIAL_DETECT_IRQ @@ -19,11 +23,13 @@ #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF #endif +#ifndef SERIAL_PORT_DFNS #define SERIAL_PORT_DFNS \ /* UART CLK PORT IRQ FLAGS */ \ { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ +#endif #endif /* _ASM_X86_SERIAL_H */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fcaabd0..ea7624c 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -143,6 +143,17 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) setup_clear_cpu_cap(X86_FEATURE_ERMS); } } + + /* + * Quark X1000 PGE is advertised but not implemented. This matters since + * cpu_has_pge is used to determine the type of TLB flushing to do. With + * PGE not actually doing what it says on the tin writes to CR4.PGE do + * nothing when we should be re-writing CR3 like a 486 + */ + if (c->x86 == 5 && c->x86_model == 9){ + printk(KERN_INFO "Disabling PGE capability bit\n"); + setup_clear_cpu_cap(X86_FEATURE_PGE); + } } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 8b24289..c963186 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -761,7 +761,10 @@ void __init setup_arch(char **cmdline_p) KERNEL_PGD_PTRS); load_cr3(swapper_pg_dir); - __flush_tlb_all(); + if (boot_cpu_data.x86 == 5 && boot_cpu_data.x86_model == 9) + __flush_tlb(); + else + __flush_tlb_all(); #else printk(KERN_INFO "Command line: %s\n", boot_command_line); #endif diff --git a/arch/x86/platform/efi/efi-bgrt.c b/arch/x86/platform/efi/efi-bgrt.c index d9c1b95..9fd5168 100644 --- a/arch/x86/platform/efi/efi-bgrt.c +++ b/arch/x86/platform/efi/efi-bgrt.c @@ -24,19 +24,29 @@ struct bmp_header { u32 size; } __packed; -void efi_bgrt_init(void) +bool __init efi_bgrt_probe(void) { acpi_status status; - void __iomem *image; - bool ioremapped = false; - struct bmp_header bmp_header; if (acpi_disabled) - return; + return false; + bgrt_tab = NULL; status = acpi_get_table("BGRT", 0, (struct acpi_table_header **)&bgrt_tab); if (ACPI_FAILURE(status)) + return false; + + return true; +} + +void __init efi_bgrt_init(void) +{ + void __iomem *image; + bool ioremapped = false; + struct bmp_header bmp_header; + + if (acpi_disabled || bgrt_tab == NULL) return; if (bgrt_tab->header.length < sizeof(*bgrt_tab)) diff --git a/include/linux/efi-bgrt.h b/include/linux/efi-bgrt.h index 051b21f..165426b 100644 --- a/include/linux/efi-bgrt.h +++ b/include/linux/efi-bgrt.h @@ -6,6 +6,7 @@ #include void efi_bgrt_init(void); +bool efi_bgrt_probe(void); /* The BGRT data itself; only valid if bgrt_image != NULL. */ extern void *bgrt_image; @@ -15,6 +16,7 @@ extern struct acpi_table_bgrt *bgrt_tab; #else /* !CONFIG_ACPI_BGRT */ static inline void efi_bgrt_init(void) {} +static inline bool efi_bgrt_probe(void) { return false; } #endif /* !CONFIG_ACPI_BGRT */