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authorTing Liu <ting.liu@nxp.com>2016-05-18 11:28:50 +0800
committerZhenhua Luo <zhenhua.luo@nxp.com>2016-06-23 10:58:15 +0800
commit69077cd2bf17e27dc681b6521cae15fef593cfc8 (patch)
tree3968cf857808481926eea7cb6258c5db35f13d11
parent41d0673b988127418e61fa7fbe141325da1af1c5 (diff)
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ipc: update to 74d6627
Changelog: af0a2a1 B4:DSP_BT: Add new DDRC target ID configuration parameter c8a84c6 B4:L1D: Add support for L1 defense New flow 8e79e5c B4:DSP_BT: DSP cache-cluster init now done from DSP boot loader 44da44a B4:DSP_BT: Add support for DSP MMU configuration Signed-off-by: Ting Liu <ting.liu@nxp.com>
-rw-r--r--recipes-bsp/ipc/ipc.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/recipes-bsp/ipc/ipc.inc b/recipes-bsp/ipc/ipc.inc
index 90eda7f..73df6ce 100644
--- a/recipes-bsp/ipc/ipc.inc
+++ b/recipes-bsp/ipc/ipc.inc
@@ -1,7 +1,7 @@
DEPENDS = "virtual/kernel"
-SRC_URI = "git://git.freescale.com/ppc/sdk/ipc.git;branch=sdk-v1.9.x"
-SRCREV = "b010e35daf0a32ee45153fc76dd392949a3097a2"
+SRC_URI = "git://git.freescale.com/ppc/sdk/ipc.git;branch=sdk-v2.0.x"
+SRCREV = "74d662707558290f070f9589177db730444bc435"
COMPATIBLE_MACHINE = "(bsc9132qds|bsc9131rdb|b4860qds|b4420qds)"