1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
From 38ff3dfb8dee467e37c1416a5c6d1cd9891426fc Mon Sep 17 00:00:00 2001
From: Junwei Zhang <Jerry.Zhang@amd.com>
Date: Wed, 10 Aug 2016 13:49:04 +0800
Subject: [PATCH 108/117] amdgpu/tests: add Polaris12 support for cs test
Change-Id: Ida31ea85ad851dbe41599a4d791ad2cbd0a14ee5
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
---
tests/amdgpu/cs_tests.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 2c9c1ae..6c4a915 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -208,8 +208,10 @@ static void amdgpu_cs_uvd_create(void)
if (family_id >= AMDGPU_FAMILY_VI) {
((uint8_t*)msg)[0x10] = 7;
/* chip polaris 10/11 */
- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A
+ || chip_id == chip_rev+0x64) {
/* dpb size */
+ printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id);
((uint8_t*)msg)[0x28] = 0x00;
((uint8_t*)msg)[0x29] = 0x94;
((uint8_t*)msg)[0x2A] = 0x6B;
@@ -286,7 +288,8 @@ static void amdgpu_cs_uvd_decode(void)
ptr[0x98] = 0x00;
ptr[0x99] = 0x02;
/* chip polaris10/11 */
- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A
+ || chip_id == chip_rev+0x64) {
/*dpb size */
ptr[0x24] = 0x00;
ptr[0x25] = 0x94;
@@ -330,7 +333,8 @@ static void amdgpu_cs_uvd_decode(void)
dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
if ((family_id >= AMDGPU_FAMILY_VI) &&
- (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+ (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A
+ || chip_id == chip_rev+0x64)) {
ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
}
@@ -344,7 +348,8 @@ static void amdgpu_cs_uvd_decode(void)
uvd_cmd(bs_addr, 0x100, &i);
if (family_id >= AMDGPU_FAMILY_VI) {
uvd_cmd(it_addr, 0x204, &i);
- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+ chip_id == chip_rev+0x64)
uvd_cmd(ctx_addr, 0x206, &i);
}
ib_cpu[i++] = 0x3BC6;
--
2.7.4
|
