1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
|
From eae6ddd03bd0a561162cfc13ec49bcbca43b8daf Mon Sep 17 00:00:00 2001
From: Amber Lin <Amber.Lin@amd.com>
Date: Thu, 13 Apr 2017 16:49:58 -0400
Subject: [PATCH 1084/4131] drm/amdgpu: handle foreign BOs in the VM mapping
Use the correct device for the PTE creation.
Bug: SWDEV-118409
Change-Id: Idf9989d122f9923702f13c3f7dd3b4d1a0796448
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9217edd..8a32c7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1646,6 +1646,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
dma_addr_t *pages_addr,
struct amdgpu_vm *vm,
struct amdgpu_bo_va_mapping *mapping,
+ uint64_t vram_base_offset,
uint64_t flags,
struct ttm_mem_reg *mem,
struct dma_fence **fence)
@@ -1702,12 +1703,12 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
max_entries = min(max_entries, 16ull * 1024ull);
break;
case AMDGPU_PL_DGMA:
- addr += adev->vm_manager.vram_base_offset +
+ addr += vram_base_offset +
adev->mman.bdev.man[mem->mem_type].gpu_offset -
adev->mman.bdev.man[TTM_PL_VRAM].gpu_offset;
break;
case TTM_PL_VRAM:
- addr += adev->vm_manager.vram_base_offset;
+ addr += vram_base_offset;
break;
default:
break;
@@ -1760,6 +1761,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+ uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+ struct amdgpu_device *bo_adev;
int r;
if (clear || !bo_va->base.bo) {
@@ -1781,9 +1784,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
- if (bo)
+ if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
- else
+ bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ if (mem && mem->mem_type == TTM_PL_VRAM &&
+ adev != bo_adev) {
+ flags |= AMDGPU_PTE_SYSTEM;
+ vram_base_offset = bo_adev->mc.aper_base;
+ }
+ } else
flags = 0x0;
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
@@ -1801,8 +1810,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_for_each_entry(mapping, &bo_va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
- mapping, flags, mem,
- last_update);
+ mapping, vram_base_offset, flags,
+ mem, last_update);
if (r)
return r;
}
--
2.7.4
|
