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From deb94b5cde8e132e3cfa552e099c5cf26c189c06 Mon Sep 17 00:00:00 2001
From: Wenjing Liu <Wenjing.Liu@amd.com>
Date: Tue, 15 Aug 2017 19:10:14 -0400
Subject: [PATCH 0984/4131] drm/amd/display: Cache edp config in dc link
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0144c98..d621237 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2258,6 +2258,8 @@ static void retrieve_link_cap(struct dc_link *link)
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
link->dpcd_caps.panel_mode_edp =
edp_config_cap.bits.ALT_SCRAMBLER_RESET;
+ link->dpcd_caps.dpcd_display_control_capable =
+ edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
link->test_pattern_enabled = false;
link->compliance_test_state.raw = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 384c72c..0f9157f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -775,6 +775,7 @@ struct dpcd_caps {
bool allow_invalid_MSA_timing_param;
bool panel_mode_edp;
+ bool dpcd_display_control_capable;
};
struct dc_link_status {
@@ -849,7 +850,6 @@ struct dc_link {
struct dpcd_caps dpcd_caps;
unsigned short chip_caps;
unsigned int dpcd_sink_count;
-
enum edp_revision edp_revision;
bool psr_enabled;
--
2.7.4
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