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From 781b80ef6f547e6568a489d215351e87030cdb8d Mon Sep 17 00:00:00 2001
From: Felix Kuehling <Felix.Kuehling@amd.com>
Date: Tue, 20 Jun 2017 17:59:29 -0400
Subject: [PATCH 0841/4131] drm/amdgpu: Make VRAM ptrace access work for
non-contiguous
Make it work for non-contiguous memory. This also fixes ptrace access
with non-0 VRAM locations where the MC address doesn't match the
physical address.
Change-Id: I2651ee47c661595d514a85d4122934561aedfc25
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index bb3cfe3..57904b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1574,10 +1574,17 @@ static int amdgpu_ttm_bo_access_vram(struct amdgpu_bo *abo,
void *buf, int len, int write)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
- uint64_t pos = amdgpu_bo_gpu_offset(abo) + offset;
+ struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
uint32_t value = 0;
- unsigned long flags;
int result = 0;
+ uint64_t pos;
+ unsigned long flags;
+
+ while (offset >= (nodes->size << PAGE_SHIFT)) {
+ offset -= nodes->size << PAGE_SHIFT;
+ ++nodes;
+ }
+ pos = (nodes->start << PAGE_SHIFT) + offset;
while (len && pos < adev->mc.mc_vram_size) {
uint64_t aligned_pos = pos & ~(uint64_t)3;
--
2.7.4
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