path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0693-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch

From 50964963594fdf8096d2a915797bef46163d86b4 Mon Sep 17 00:00:00 2001
From: Yue Hin Lau <Yuehin.Lau@amd.com>
Date: Tue, 25 Jul 2017 16:45:18 -0400
Subject: [PATCH 0693/4131] drm/amd/display: move ocsc programming from opp to
 dpp for dce

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c       | 201 +-------------------
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h       |  31 ---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 210 +++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h |  30 +++
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  35 +++-
 .../drm/amd/display/dc/dce110/dce110_opp_csc_v.c   |  45 +++--
 .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c   |   2 -
 .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h   |   6 -
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |   2 +
 .../drm/amd/display/dc/dce110/dce110_transform_v.h |   7 +
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h        |   7 +-
 11 files changed, 306 insertions(+), 270 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index f716a9e..7abf252 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -55,31 +55,9 @@ enum {
 	OUTPUT_CSC_MATRIX_SIZE = 12
 };
 
-static const struct out_csc_color_matrix global_color_matrix[] = {
-{ COLOR_SPACE_SRGB,
-	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-{ COLOR_SPACE_SRGB_LIMITED,
-	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-{ COLOR_SPACE_YCBCR601,
-	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-		0xF6B9, 0xE00, 0x1000} },
-{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-/* TODO: correct values below */
-{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-};
 
-enum csc_color_mode {
-	/* 00 - BITS2:0 Bypass */
-	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-	/* 01 - hard coded coefficient TV RGB */
-	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-	/* 04 - programmable OUTPUT CSC coefficient */
-	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-};
+
+
 
 
 
@@ -781,181 +759,8 @@ void dce110_opp_program_fmt(
 	return;
 }
 
-static void program_color_matrix(
-	struct dce110_opp *opp110,
-	const struct out_csc_color_matrix *tbl_entry,
-	enum grph_color_adjust_option options)
-{
-	{
-		REG_SET_2(OUTPUT_CSC_C11_C12, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[0],
-			OUTPUT_CSC_C12, tbl_entry->regval[1]);
-	}
-	{
-		REG_SET_2(OUTPUT_CSC_C13_C14, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[2],
-			OUTPUT_CSC_C12, tbl_entry->regval[3]);
-	}
-	{
-		REG_SET_2(OUTPUT_CSC_C21_C22, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[4],
-			OUTPUT_CSC_C12, tbl_entry->regval[5]);
-	}
-	{
-		REG_SET_2(OUTPUT_CSC_C23_C24, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[6],
-			OUTPUT_CSC_C12, tbl_entry->regval[7]);
-	}
-	{
-		REG_SET_2(OUTPUT_CSC_C31_C32, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[8],
-			OUTPUT_CSC_C12, tbl_entry->regval[9]);
-	}
-	{
-		REG_SET_2(OUTPUT_CSC_C33_C34, 0,
-			OUTPUT_CSC_C11, tbl_entry->regval[10],
-			OUTPUT_CSC_C12, tbl_entry->regval[11]);
-	}
-}
 
-static bool configure_graphics_mode(
-	struct dce110_opp *opp110,
-	enum csc_color_mode config,
-	enum graphics_csc_adjust_type csc_adjust_type,
-	enum dc_color_space color_space)
-{
-	REG_SET(OUTPUT_CSC_CONTROL, 0,
-		OUTPUT_CSC_GRPH_MODE, 0);
 
-	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
-			REG_SET(OUTPUT_CSC_CONTROL, 0,
-				OUTPUT_CSC_GRPH_MODE, 4);
-		} else {
-
-			switch (color_space) {
-			case COLOR_SPACE_SRGB:
-				/* by pass */
-				REG_SET(OUTPUT_CSC_CONTROL, 0,
-					OUTPUT_CSC_GRPH_MODE, 0);
-				break;
-			case COLOR_SPACE_SRGB_LIMITED:
-				/* TV RGB */
-				REG_SET(OUTPUT_CSC_CONTROL, 0,
-					OUTPUT_CSC_GRPH_MODE, 1);
-				break;
-			case COLOR_SPACE_YCBCR601:
-			case COLOR_SPACE_YCBCR601_LIMITED:
-				/* YCbCr601 */
-				REG_SET(OUTPUT_CSC_CONTROL, 0,
-					OUTPUT_CSC_GRPH_MODE, 2);
-				break;
-			case COLOR_SPACE_YCBCR709:
-			case COLOR_SPACE_YCBCR709_LIMITED:
-				/* YCbCr709 */
-				REG_SET(OUTPUT_CSC_CONTROL, 0,
-					OUTPUT_CSC_GRPH_MODE, 3);
-				break;
-			default:
-				return false;
-			}
-		}
-	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-		switch (color_space) {
-		case COLOR_SPACE_SRGB:
-			/* by pass */
-			REG_SET(OUTPUT_CSC_CONTROL, 0,
-				OUTPUT_CSC_GRPH_MODE, 0);
-			break;
-			break;
-		case COLOR_SPACE_SRGB_LIMITED:
-			/* TV RGB */
-			REG_SET(OUTPUT_CSC_CONTROL, 0,
-				OUTPUT_CSC_GRPH_MODE, 1);
-			break;
-		case COLOR_SPACE_YCBCR601:
-		case COLOR_SPACE_YCBCR601_LIMITED:
-			/* YCbCr601 */
-			REG_SET(OUTPUT_CSC_CONTROL, 0,
-				OUTPUT_CSC_GRPH_MODE, 2);
-			break;
-		case COLOR_SPACE_YCBCR709:
-		case COLOR_SPACE_YCBCR709_LIMITED:
-			 /* YCbCr709 */
-			REG_SET(OUTPUT_CSC_CONTROL, 0,
-				OUTPUT_CSC_GRPH_MODE, 3);
-			break;
-		default:
-			return false;
-		}
-
-	} else
-		/* by pass */
-		REG_SET(OUTPUT_CSC_CONTROL, 0,
-			OUTPUT_CSC_GRPH_MODE, 0);
-
-	return true;
-}
-
-void dce110_opp_set_csc_adjustment(
-	struct output_pixel_processor *opp,
-	const struct out_csc_color_matrix *tbl_entry)
-{
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-	enum csc_color_mode config =
-			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-
-	program_color_matrix(
-			opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
-
-	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-	configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
-			tbl_entry->color_space);
-}
-
-void dce110_opp_set_csc_default(
-	struct output_pixel_processor *opp,
-	const struct default_adjustment *default_adjust)
-{
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-	enum csc_color_mode config =
-			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-
-	if (default_adjust->force_hw_default == false) {
-		const struct out_csc_color_matrix *elm;
-		/* currently parameter not in use */
-		enum grph_color_adjust_option option =
-			GRPH_COLOR_MATRIX_HW_DEFAULT;
-		uint32_t i;
-		/*
-		 * HW default false we program locally defined matrix
-		 * HW default true  we use predefined hw matrix and we
-		 * do not need to program matrix
-		 * OEM wants the HW default via runtime parameter.
-		 */
-		option = GRPH_COLOR_MATRIX_SW;
-
-		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-			elm = &global_color_matrix[i];
-			if (elm->color_space != default_adjust->out_color_space)
-				continue;
-			/* program the matrix with default values from this
-			 * file */
-			program_color_matrix(opp110, elm, option);
-			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-			break;
-		}
-	}
-
-	/* configure the what we programmed :
-	 * 1. Default values from this file
-	 * 2. Use hardware default from ROM_A and we do not need to program
-	 * matrix */
-
-	configure_graphics_mode(opp110, config,
-		default_adjust->csc_adjust_type,
-		default_adjust->out_color_space);
-}
 
 
 /*****************************************/
@@ -964,8 +769,6 @@ void dce110_opp_set_csc_default(
 
 static const struct opp_funcs funcs = {
 	.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
-	.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
-	.opp_set_csc_default = dce110_opp_set_csc_default,
 	.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
 	.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
 	.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index e5045d2..ca09f52 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -57,13 +57,6 @@ enum dce110_opp_reg_type {
 	SRI(REGAMMA_LUT_INDEX, DCP, id), \
 	SRI(REGAMMA_LUT_DATA, DCP, id), \
 	SRI(REGAMMA_CONTROL, DCP, id), \
-	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
-	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
-	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
-	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
-	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
-	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
-	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
 	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
 	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
 	SRI(FMT_CONTROL, FMT, id), \
@@ -129,9 +122,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
 	OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
 	OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
-	OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
-	OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
-	OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
 	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
 	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
 	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
@@ -222,9 +212,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
 	OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
 	OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
-	OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
-	OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
-	OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
 	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
 	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
 	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
@@ -288,9 +275,6 @@ enum dce110_opp_reg_type {
 	type REGAMMA_LUT_MEM_PWR_STATE; \
 	type REGAMMA_LUT_WRITE_EN_MASK; \
 	type GRPH_REGAMMA_MODE; \
-	type OUTPUT_CSC_C11; \
-	type OUTPUT_CSC_C12; \
-	type OUTPUT_CSC_GRPH_MODE; \
 	type FMT_DYNAMIC_EXP_EN; \
 	type FMT_DYNAMIC_EXP_MODE; \
 	type FMT_TRUNCATE_EN; \
@@ -362,13 +346,6 @@ struct dce_opp_registers {
 	uint32_t DCFE_MEM_PWR_STATUS;
 	uint32_t REGAMMA_LUT_DATA;
 	uint32_t REGAMMA_CONTROL;
-	uint32_t OUTPUT_CSC_C11_C12;
-	uint32_t OUTPUT_CSC_C13_C14;
-	uint32_t OUTPUT_CSC_C21_C22;
-	uint32_t OUTPUT_CSC_C23_C24;
-	uint32_t OUTPUT_CSC_C31_C32;
-	uint32_t OUTPUT_CSC_C33_C34;
-	uint32_t OUTPUT_CSC_CONTROL;
 	uint32_t FMT_DYNAMIC_EXP_CNTL;
 	uint32_t FMT_BIT_DEPTH_CONTROL;
 	uint32_t FMT_CONTROL;
@@ -417,14 +394,6 @@ bool dce110_opp_program_regamma_pwl(
 void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
 		enum opp_regamma mode);
 
-void dce110_opp_set_csc_adjustment(
-	struct output_pixel_processor *opp,
-	const struct out_csc_color_matrix *tbl_entry);
-
-void dce110_opp_set_csc_default(
-	struct output_pixel_processor *opp,
-	const struct default_adjustment *default_adjust);
-
 /* FORMATTER RELATED */
 void dce110_opp_program_bit_depth_reduction(
 	struct output_pixel_processor *opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index c861fd7..fb64dca4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -80,6 +80,37 @@ enum dcp_spatial_dither_depth {
 	DCP_SPATIAL_DITHER_DEPTH_24BPP
 };
 
+enum csc_color_mode {
+	/* 00 - BITS2:0 Bypass */
+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
+	/* 01 - hard coded coefficient TV RGB */
+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
+	/* 04 - programmable OUTPUT CSC coefficient */
+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
+};
+
+enum grph_color_adjust_option {
+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
+	GRPH_COLOR_MATRIX_SW
+};
+
+static const struct out_csc_color_matrix global_color_matrix[] = {
+{ COLOR_SPACE_SRGB,
+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+{ COLOR_SPACE_SRGB_LIMITED,
+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
+{ COLOR_SPACE_YCBCR601,
+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
+		0xF6B9, 0xE00, 0x1000} },
+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
+/* TODO: correct values below */
+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
+};
+
 static bool setup_scaling_configuration(
 	struct dce_transform *xfm_dce,
 	const struct scaler_data *data)
@@ -970,6 +1001,183 @@ static void dce_transform_reset(struct transform *xfm)
 	xfm_dce->filter_v = NULL;
 }
 
+static void program_color_matrix(
+	struct dce_transform *xfm_dce,
+	const struct out_csc_color_matrix *tbl_entry,
+	enum grph_color_adjust_option options)
+{
+	{
+		REG_SET_2(OUTPUT_CSC_C11_C12, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[0],
+			OUTPUT_CSC_C12, tbl_entry->regval[1]);
+	}
+	{
+		REG_SET_2(OUTPUT_CSC_C13_C14, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[2],
+			OUTPUT_CSC_C12, tbl_entry->regval[3]);
+	}
+	{
+		REG_SET_2(OUTPUT_CSC_C21_C22, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[4],
+			OUTPUT_CSC_C12, tbl_entry->regval[5]);
+	}
+	{
+		REG_SET_2(OUTPUT_CSC_C23_C24, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[6],
+			OUTPUT_CSC_C12, tbl_entry->regval[7]);
+	}
+	{
+		REG_SET_2(OUTPUT_CSC_C31_C32, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[8],
+			OUTPUT_CSC_C12, tbl_entry->regval[9]);
+	}
+	{
+		REG_SET_2(OUTPUT_CSC_C33_C34, 0,
+			OUTPUT_CSC_C11, tbl_entry->regval[10],
+			OUTPUT_CSC_C12, tbl_entry->regval[11]);
+	}
+}
+
+static bool configure_graphics_mode(
+	struct dce_transform *xfm_dce,
+	enum csc_color_mode config,
+	enum graphics_csc_adjust_type csc_adjust_type,
+	enum dc_color_space color_space)
+{
+	REG_SET(OUTPUT_CSC_CONTROL, 0,
+		OUTPUT_CSC_GRPH_MODE, 0);
+
+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
+			REG_SET(OUTPUT_CSC_CONTROL, 0,
+				OUTPUT_CSC_GRPH_MODE, 4);
+		} else {
+
+			switch (color_space) {
+			case COLOR_SPACE_SRGB:
+				/* by pass */
+				REG_SET(OUTPUT_CSC_CONTROL, 0,
+					OUTPUT_CSC_GRPH_MODE, 0);
+				break;
+			case COLOR_SPACE_SRGB_LIMITED:
+				/* TV RGB */
+				REG_SET(OUTPUT_CSC_CONTROL, 0,
+					OUTPUT_CSC_GRPH_MODE, 1);
+				break;
+			case COLOR_SPACE_YCBCR601:
+			case COLOR_SPACE_YCBCR601_LIMITED:
+				/* YCbCr601 */
+				REG_SET(OUTPUT_CSC_CONTROL, 0,
+					OUTPUT_CSC_GRPH_MODE, 2);
+				break;
+			case COLOR_SPACE_YCBCR709:
+			case COLOR_SPACE_YCBCR709_LIMITED:
+				/* YCbCr709 */
+				REG_SET(OUTPUT_CSC_CONTROL, 0,
+					OUTPUT_CSC_GRPH_MODE, 3);
+				break;
+			default:
+				return false;
+			}
+		}
+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
+		switch (color_space) {
+		case COLOR_SPACE_SRGB:
+			/* by pass */
+			REG_SET(OUTPUT_CSC_CONTROL, 0,
+				OUTPUT_CSC_GRPH_MODE, 0);
+			break;
+			break;
+		case COLOR_SPACE_SRGB_LIMITED:
+			/* TV RGB */
+			REG_SET(OUTPUT_CSC_CONTROL, 0,
+				OUTPUT_CSC_GRPH_MODE, 1);
+			break;
+		case COLOR_SPACE_YCBCR601:
+		case COLOR_SPACE_YCBCR601_LIMITED:
+			/* YCbCr601 */
+			REG_SET(OUTPUT_CSC_CONTROL, 0,
+				OUTPUT_CSC_GRPH_MODE, 2);
+			break;
+		case COLOR_SPACE_YCBCR709:
+		case COLOR_SPACE_YCBCR709_LIMITED:
+			 /* YCbCr709 */
+			REG_SET(OUTPUT_CSC_CONTROL, 0,
+				OUTPUT_CSC_GRPH_MODE, 3);
+			break;
+		default:
+			return false;
+		}
+
+	} else
+		/* by pass */
+		REG_SET(OUTPUT_CSC_CONTROL, 0,
+			OUTPUT_CSC_GRPH_MODE, 0);
+
+	return true;
+}
+
+void dce110_opp_set_csc_adjustment(
+	struct transform *xfm,
+	const struct out_csc_color_matrix *tbl_entry)
+{
+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
+	enum csc_color_mode config =
+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
+
+	program_color_matrix(
+			xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
+
+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
+	configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
+			tbl_entry->color_space);
+}
+
+void dce110_opp_set_csc_default(
+	struct transform *xfm,
+	const struct default_adjustment *default_adjust)
+{
+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
+	enum csc_color_mode config =
+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
+
+	if (default_adjust->force_hw_default == false) {
+		const struct out_csc_color_matrix *elm;
+		/* currently parameter not in use */
+		enum grph_color_adjust_option option =
+			GRPH_COLOR_MATRIX_HW_DEFAULT;
+		uint32_t i;
+		/*
+		 * HW default false we program locally defined matrix
+		 * HW default true  we use predefined hw matrix and we
+		 * do not need to program matrix
+		 * OEM wants the HW default via runtime parameter.
+		 */
+		option = GRPH_COLOR_MATRIX_SW;
+
+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
+			elm = &global_color_matrix[i];
+			if (elm->color_space != default_adjust->out_color_space)
+				continue;
+			/* program the matrix with default values from this
+			 * file */
+			program_color_matrix(xfm_dce, elm, option);
+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
+			break;
+		}
+	}
+
+	/* configure the what we programmed :
+	 * 1. Default values from this file
+	 * 2. Use hardware default from ROM_A and we do not need to program
+	 * matrix */
+
+	configure_graphics_mode(xfm_dce, config,
+		default_adjust->csc_adjust_type,
+		default_adjust->out_color_space);
+}
+
+
 
 static const struct transform_funcs dce_transform_funcs = {
 	.transform_reset = dce_transform_reset,
@@ -977,6 +1185,8 @@ static const struct transform_funcs dce_transform_funcs = {
 		dce_transform_set_scaler,
 	.transform_set_gamut_remap =
 		dce_transform_set_gamut_remap,
+	.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
+	.opp_set_csc_default = dce110_opp_set_csc_default,
 	.transform_set_pixel_storage_depth =
 		dce_transform_set_pixel_storage_depth,
 	.transform_get_optimal_number_of_taps =
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
index ca6c621..8632d8f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
@@ -44,6 +44,13 @@
 	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
 	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
 	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
+	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
+	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
+	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
+	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
+	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
+	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
+	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
 	SRI(DENORM_CONTROL, DCP, id), \
 	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
 	SRI(OUT_ROUND_CONTROL, DCP, id), \
@@ -114,6 +121,9 @@
 	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
 	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
 	XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
+	XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
 	XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
 	XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
 	XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
@@ -183,6 +193,9 @@
 	XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
 	XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
 	XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
+	XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
+	XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
+	XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
 	XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
 	XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
 	XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
@@ -249,6 +262,9 @@
 	type GAMUT_REMAP_C33; \
 	type GAMUT_REMAP_C34; \
 	type GRPH_GAMUT_REMAP_MODE; \
+	type OUTPUT_CSC_C11; \
+	type OUTPUT_CSC_C12; \
+	type OUTPUT_CSC_GRPH_MODE; \
 	type SCL_MODE; \
 	type SCL_BYPASS_MODE; \
 	type SCL_PSCL_EN; \
@@ -302,6 +318,13 @@ struct dce_transform_registers {
 	uint32_t GAMUT_REMAP_C23_C24;
 	uint32_t GAMUT_REMAP_C31_C32;
 	uint32_t GAMUT_REMAP_C33_C34;
+	uint32_t OUTPUT_CSC_C11_C12;
+	uint32_t OUTPUT_CSC_C13_C14;
+	uint32_t OUTPUT_CSC_C21_C22;
+	uint32_t OUTPUT_CSC_C23_C24;
+	uint32_t OUTPUT_CSC_C31_C32;
+	uint32_t OUTPUT_CSC_C33_C34;
+	uint32_t OUTPUT_CSC_CONTROL;
 	uint32_t DENORM_CONTROL;
 	uint32_t DCP_SPATIAL_DITHER_CNTL;
 	uint32_t OUT_ROUND_CONTROL;
@@ -381,5 +404,12 @@ bool dce_transform_get_optimal_number_of_taps(
 	struct scaler_data *scl_data,
 	const struct scaling_taps *in_taps);
 
+void dce110_opp_set_csc_adjustment(
+	struct transform *xfm,
+	const struct out_csc_color_matrix *tbl_entry);
+
+void dce110_opp_set_csc_default(
+	struct transform *xfm,
+	const struct default_adjustment *default_adjust);
 
 #endif /* _DCE_DCE_TRANSFORM_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6afe572c..ad831e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1868,8 +1868,8 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
 	/* Lb color depth */
 	default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth;
 
-	pipe_ctx->opp->funcs->opp_set_csc_default(
-					pipe_ctx->opp, &default_adjust);
+	pipe_ctx->xfm->funcs->opp_set_csc_default(
+					pipe_ctx->xfm, &default_adjust);
 }
 
 
@@ -1991,8 +1991,8 @@ static void set_plane_config(
 			tbl_entry.regval[i] =
 			pipe_ctx->stream->csc_color_matrix.matrix[i];
 
-		pipe_ctx->opp->funcs->opp_set_csc_adjustment
-				(pipe_ctx->opp, &tbl_entry);
+		pipe_ctx->xfm->funcs->opp_set_csc_adjustment
+				(pipe_ctx->xfm, &tbl_entry);
 	}
 
 	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
@@ -2446,8 +2446,8 @@ static void dce110_program_front_end_for_pipe(
 			tbl_entry.regval[i] =
 			pipe_ctx->stream->csc_color_matrix.matrix[i];
 
-		pipe_ctx->opp->funcs->opp_set_csc_adjustment
-				(pipe_ctx->opp, &tbl_entry);
+		pipe_ctx->xfm->funcs->opp_set_csc_adjustment
+				(pipe_ctx->xfm, &tbl_entry);
 	}
 
 	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
@@ -2587,8 +2587,31 @@ static void dce110_wait_for_mpcc_disconnect(
 	/* do nothing*/
 }
 
+static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
+		enum dc_color_space colorspace,
+		uint16_t *matrix)
+{
+	int i;
+	struct out_csc_color_matrix tbl_entry;
+
+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
+				== true) {
+			enum dc_color_space color_space =
+				pipe_ctx->stream->output_color_space;
+
+			//uint16_t matrix[12];
+			for (i = 0; i < 12; i++)
+				tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
+
+			tbl_entry.color_space = color_space;
+			//tbl_entry.regval = matrix;
+			pipe_ctx->xfm->funcs->opp_set_csc_adjustment(pipe_ctx->xfm, &tbl_entry);
+	}
+}
+
 static const struct hw_sequencer_funcs dce110_funcs = {
 	.program_gamut_remap = program_gamut_remap,
+	.program_csc_matrix = program_csc_matrix,
 	.init_hw = init_hw,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
index 019effe..feb397b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
@@ -24,7 +24,7 @@
  */
 
 #include "dm_services.h"
-#include "dce/dce_opp.h"
+#include "dce110_transform_v.h"
 #include "basics/conversion.h"
 
 /* include DCE11 register header files */
@@ -100,12 +100,17 @@ enum csc_color_mode {
 	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
 };
 
+enum grph_color_adjust_option {
+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
+	GRPH_COLOR_MATRIX_SW
+};
+
 static void program_color_matrix_v(
-	struct dce110_opp *opp110,
+	struct dce_transform *xfm_dce,
 	const struct out_csc_color_matrix *tbl_entry,
 	enum grph_color_adjust_option options)
 {
-	struct dc_context *ctx = opp110->base.ctx;
+	struct dc_context *ctx = xfm_dce->base.ctx;
 	uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
 	bool use_set_a = (get_reg_field_value(cntl_value,
 			COL_MAN_OUTPUT_CSC_CONTROL,
@@ -351,12 +356,12 @@ static void program_color_matrix_v(
 }
 
 static bool configure_graphics_mode_v(
-	struct dce110_opp *opp110,
+	struct dce_transform *xfm_dce,
 	enum csc_color_mode config,
 	enum graphics_csc_adjust_type csc_adjust_type,
 	enum dc_color_space color_space)
 {
-	struct dc_context *ctx = opp110->base.ctx;
+	struct dc_context *ctx = xfm_dce->base.ctx;
 	uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
 	uint32_t value = dm_read_reg(ctx, addr);
 
@@ -454,10 +459,10 @@ static bool configure_graphics_mode_v(
 }
 
 /*TODO: color depth is not correct when this is called*/
-static void set_Denormalization(struct output_pixel_processor *opp,
+static void set_Denormalization(struct transform *xfm,
 		enum dc_color_depth color_depth)
 {
-	uint32_t value = dm_read_reg(opp->ctx, mmDENORM_CLAMP_CONTROL);
+	uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL);
 
 	switch (color_depth) {
 	case COLOR_DEPTH_888:
@@ -495,7 +500,7 @@ static void set_Denormalization(struct output_pixel_processor *opp,
 		DENORM_CLAMP_CONTROL,
 		DENORM_10BIT_OUT);
 
-	dm_write_reg(opp->ctx, mmDENORM_CLAMP_CONTROL, value);
+	dm_write_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL, value);
 }
 
 struct input_csc_matrix {
@@ -524,10 +529,10 @@ static const struct input_csc_matrix input_csc_matrix[] = {
 };
 
 static void program_input_csc(
-	struct output_pixel_processor *opp, enum dc_color_space color_space)
+		struct transform *xfm, enum dc_color_space color_space)
 {
 	int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix);
-	struct dc_context *ctx = opp->ctx;
+	struct dc_context *ctx = xfm->ctx;
 	const uint32_t *regval = NULL;
 	bool use_set_a;
 	uint32_t value;
@@ -664,10 +669,10 @@ static void program_input_csc(
 }
 
 void dce110_opp_v_set_csc_default(
-	struct output_pixel_processor *opp,
+	struct transform *xfm,
 	const struct default_adjustment *default_adjust)
 {
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 	enum csc_color_mode config =
 			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
 
@@ -692,13 +697,13 @@ void dce110_opp_v_set_csc_default(
 			/* program the matrix with default values from this
 			 * file
 			 */
-			program_color_matrix_v(opp110, elm, option);
+			program_color_matrix_v(xfm_dce, elm, option);
 			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
 			break;
 		}
 	}
 
-	program_input_csc(opp, default_adjust->in_color_space);
+	program_input_csc(xfm, default_adjust->in_color_space);
 
 	/* configure the what we programmed :
 	 * 1. Default values from this file
@@ -706,26 +711,26 @@ void dce110_opp_v_set_csc_default(
 	 * matrix
 	 */
 
-	configure_graphics_mode_v(opp110, config,
+	configure_graphics_mode_v(xfm_dce, config,
 		default_adjust->csc_adjust_type,
 		default_adjust->out_color_space);
 
-	set_Denormalization(opp, default_adjust->color_depth);
+	set_Denormalization(xfm, default_adjust->color_depth);
 }
 
 void dce110_opp_v_set_csc_adjustment(
-	struct output_pixel_processor *opp,
+	struct transform *xfm,
 	const struct out_csc_color_matrix *tbl_entry)
 {
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 	enum csc_color_mode config =
 			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
 
 	program_color_matrix_v(
-			opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
+			xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
 
 	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-	configure_graphics_mode_v(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
+	configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
 			tbl_entry->color_space);
 
 	/*TODO: Check if denormalization is needed*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
index 6f8b414..24d9032f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
@@ -39,8 +39,6 @@
 static const struct opp_funcs funcs = {
 		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
 		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
-		.opp_set_csc_default = dce110_opp_v_set_csc_default,
-		.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
 		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
 		.opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
 		.opp_destroy = dce110_opp_destroy,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
index cb26c51..7deaa4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
@@ -33,13 +33,7 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110,
 	struct dc_context *ctx);
 
 /* underlay callbacks */
-void dce110_opp_v_set_csc_default(
-	struct output_pixel_processor *opp,
-	const struct default_adjustment *default_adjust);
 
-void dce110_opp_v_set_csc_adjustment(
-	struct output_pixel_processor *opp,
-	const struct out_csc_color_matrix *tbl_entry);
 
 bool dce110_opp_program_regamma_pwl_v(
 	struct output_pixel_processor *opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 8548248..f655145 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -681,6 +681,8 @@ static const struct transform_funcs dce110_xfmv_funcs = {
 	.transform_set_scaler = dce110_xfmv_set_scaler,
 	.transform_set_gamut_remap =
 		dce110_xfmv_set_gamut_remap,
+	.opp_set_csc_default = dce110_opp_v_set_csc_default,
+	.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
 	.transform_set_pixel_storage_depth =
 			dce110_xfmv_set_pixel_storage_depth,
 	.transform_get_optimal_number_of_taps =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
index 267af34..b7f8fdb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
@@ -34,4 +34,11 @@ bool dce110_transform_v_construct(
 	struct dce_transform *xfm110,
 	struct dc_context *ctx);
 
+void dce110_opp_v_set_csc_default(
+	struct transform *xfm,
+	const struct default_adjustment *default_adjust);
+
+void dce110_opp_v_set_csc_adjustment(
+		struct transform *xfm,
+	const struct out_csc_color_matrix *tbl_entry);
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 01d6957..a4f8556 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -217,13 +217,8 @@ enum fmt_stereo_action {
 	FMT_STEREO_ACTION_UPDATE_POLARITY
 };
 
-enum grph_color_adjust_option {
-	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-	GRPH_COLOR_MATRIX_SW
-};
-
 struct opp_grph_csc_adjustment {
-	enum grph_color_adjust_option color_adjust_option;
+	//enum grph_color_adjust_option color_adjust_option;
 	enum dc_color_space c_space;
 	enum dc_color_depth color_depth; /* clean up to uint32_t */
 	enum graphics_csc_adjust_type   csc_adjust_type;
-- 
2.7.4