1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
From 34c34f3a83f8834ee27a6156e28e3220a61abf30 Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Fri, 7 Jul 2017 11:24:13 -0400
Subject: [PATCH 0598/4131] drm/amd/display: dal1.1 hwseq prog update
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 223bb79..4c39bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
plane_id,
dppclk_div);
- if (dppclk_div) {
- /* 1/2 DISPCLK*/
+ if (hws->shifts->DPPCLK_RATE_CONTROL)
REG_UPDATE_2(DPP_CONTROL[plane_id],
- DPPCLK_RATE_CONTROL, 1,
+ DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
- } else {
- /* DISPCLK */
- REG_UPDATE_2(DPP_CONTROL[plane_id],
- DPPCLK_RATE_CONTROL, 0,
+ else
+ REG_UPDATE(DPP_CONTROL[plane_id],
DPP_CLOCK_ENABLE, 1);
- }
}
static void enable_power_gating_plane(
--
2.7.4
|