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From e32a0c4d32b49e780358629763fc77ef057e997b Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Wed, 5 Jul 2017 12:00:28 -0400
Subject: [PATCH 0593/4131] drm/amd/display: get dal1.1 to run
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 761dba3..6985a46 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -275,7 +275,7 @@ struct dce_hwseq_registers {
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
- HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_),\
+ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index e6f2220..669ac4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -784,7 +784,7 @@ static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
}
}
-void oppn10_set_output_csc_adjustment(
+static void oppn10_set_output_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry)
{
--
2.7.4
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