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From fc9d359f31b73eca81ab78fe5aa43fdbeeecbbe8 Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Fri, 2 Jun 2017 19:01:37 -0400
Subject: [PATCH 0504/4131] drm/amd/display: propagate surface alpha setting
from OS to DC
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++++-
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 6 ++++--
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++------
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 657e10b..fb5bacb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -998,6 +998,7 @@ bool dc_commit_surfaces_to_stream(
plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
plane_info[i].visible = new_surfaces[i]->visible;
+ plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
plane_info[i].dcc = new_surfaces[i]->dcc;
scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
scaling_info[i].src_rect = new_surfaces[i]->src_rect;
@@ -1068,7 +1069,7 @@ static enum surface_update_type get_plane_info_update_type(
const struct dc_surface_update *u,
int surface_index)
{
- struct dc_plane_info temp_plane_info = { { { { 0 } } } };
+ struct dc_plane_info temp_plane_info = { 0 };
if (!u->plane_info)
return UPDATE_TYPE_FAST;
@@ -1091,6 +1092,7 @@ static enum surface_update_type get_plane_info_update_type(
/* Special Validation parameters */
temp_plane_info.format = u->plane_info->format;
+ temp_plane_info.per_pixel_alpha = u->plane_info->per_pixel_alpha;
if (surface_index == 0)
temp_plane_info.visible = u->plane_info->visible;
@@ -1327,6 +1329,8 @@ void dc_update_surfaces_and_stream(struct dc *dc,
srf_updates[i].plane_info->tiling_info;
surface->public.visible =
srf_updates[i].plane_info->visible;
+ surface->public.per_pixel_alpha =
+ srf_updates[i].plane_info->per_pixel_alpha;
surface->public.dcc =
srf_updates[i].plane_info->dcc;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index ee840e7..c60b59f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -221,10 +221,12 @@ void update_surface_trace(
SURFACE_TRACE(
"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
"plane_info->tiling_info.gfx8.array_mode = %d;\n"
- "plane_info->visible = %d;\n",
+ "plane_info->visible = %d;\n"
+ "plane_info->per_pixel_alpha = %d;\n",
update->plane_info->tiling_info.gfx8.pipe_config,
update->plane_info->tiling_info.gfx8.array_mode,
- update->plane_info->visible);
+ update->plane_info->visible,
+ update->plane_info->per_pixel_alpha);
SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
update->plane_info->tiling_info.gfx9.swizzle);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a20ba01..7191b25 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -290,6 +290,7 @@ struct dc_transfer_func {
};
struct dc_surface {
+ bool per_pixel_alpha;
bool visible;
bool flip_immediate;
struct dc_plane_address address;
@@ -316,6 +317,7 @@ struct dc_surface {
};
struct dc_plane_info {
+ bool per_pixel_alpha;
union plane_size plane_size;
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 06354c3..5269796 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -97,7 +97,7 @@ struct dc_context {
#define MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
-#define MAX_SURFACE_NUM 2
+#define MAX_SURFACE_NUM 4
#define NUM_PIXEL_FORMATS 10
#include "dc_ddc_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 107f82d..0a346aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1559,7 +1559,9 @@ static void update_dchubp_dpp(
struct pipe_ctx *temp_pipe;
int i;
int tree_pos = 0;
+ bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe;
+ /* TODO: proper fix once fpga works */
/* depends on DML calculation, DPP clock value may change dynamically */
enable_dppclk(
dc->ctx,
@@ -1604,11 +1606,7 @@ static void update_dchubp_dpp(
/* TODO: build stream pipes group id. For now, use stream otg
* id as pipe group id
*/
- /*pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->surface->public.per_pixel_alpha;*/
- if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface)
- pipe_ctx->scl_data.lb_params.alpha_en = 1;
- else
- pipe_ctx->scl_data.lb_params.alpha_en = 0;
+ pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha;
pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
if (tree_cfg->num_pipes == 0) {
@@ -1625,7 +1623,7 @@ static void update_dchubp_dpp(
tree_cfg->dpp[tree_pos] = pipe_ctx->pipe_idx;
tree_cfg->mpcc[tree_pos] = pipe_ctx->pipe_idx;
- tree_cfg->per_pixel_alpha[tree_pos] = pipe_ctx->scl_data.lb_params.alpha_en;
+ tree_cfg->per_pixel_alpha[tree_pos] = per_pixel_alpha;
tree_cfg->num_pipes = tree_pos + 1;
dcn10_set_mpc_tree(mpc, tree_cfg);
--
2.7.4
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