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From 5f64f2dd74bc188895fe044017e44e1c966a1ab9 Mon Sep 17 00:00:00 2001
From: Hersen Wu <hersenxs.wu@amd.com>
Date: Thu, 1 Jun 2017 15:49:16 -0400
Subject: [PATCH 0496/4131] drm/amd/display: remove disable_clk_gate debug flag
for DCN
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 30 ----------------------
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 -
2 files changed, 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 877e2b6..0e677f9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -397,19 +397,6 @@ static void enable_power_gating_plane(
HWSEQ_REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
HWSEQ_REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
HWSEQ_REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
-
- if (ctx->dc->debug.disable_clock_gate) {
- /* probably better to just write entire register to 0xffff to
- * ensure all clock gating is disabled
- */
- HWSEQ_REG_UPDATE_3(DCCG_GATE_DISABLE_CNTL,
- DISPCLK_R_DCCG_GATE_DISABLE, 1,
- DPREFCLK_R_DCCG_GATE_DISABLE, 1,
- REFCLK_R_DIG_GATE_DISABLE, 1);
- HWSEQ_REG_UPDATE(DCFCLK_CNTL,
- DCFCLK_GATE_DIS, 1);
- }
-
}
static void dpp_pg_control(
@@ -513,29 +500,12 @@ static void power_on_plane(
{
uint32_t inst_offset = 0;
- /* disable clock power gating */
-
- /* DCCG_GATE_DISABLE_CNTL only has one instance */
- if (ctx->dc->debug.disable_clock_gate) {
- HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
- DISPCLK_DCCG_GATE_DISABLE, 1,
- DPPCLK_GATE_DISABLE, 1);
- /* DCFCLK_CNTL only has one instance */
- HWSEQ_REG_UPDATE(DCFCLK_CNTL,
- DCFCLK_GATE_DIS, 1);
- }
-
HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
IP_REQUEST_EN, 1);
dpp_pg_control(ctx, plane_id, true);
hubp_pg_control(ctx, plane_id, true);
HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
IP_REQUEST_EN, 0);
-
- if (ctx->dc->debug.disable_clock_gate) {
- HWSEQ_REG_UPDATE(DCCG_GATE_DISABLE_CNTL,
- DISPCLK_DCCG_GATE_DISABLE, 0);
- }
}
/* fully check bios enabledisplaypowergating table. dal only need dce init
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 660cb43..e527d10 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -438,7 +438,6 @@ static const struct dc_debug debug_defaults_drv = {
};
static const struct dc_debug debug_defaults_diags = {
- .disable_clock_gate = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = true,
--
2.7.4
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