aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch
blob: 8a90c7f5bd956d1761a4fead769324bbeacf34ae (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
From c9eab86a7238e1a783108c357562ddd7eee6acba Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Thu, 18 May 2017 16:56:45 -0400
Subject: [PATCH 0456/4131] drm/amd/display: fix flip register write sequence

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 56 ++++++++++------------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  2 +
 2 files changed, 28 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index a52c614..da2f99d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -237,7 +237,7 @@ static bool mem_input_program_surface_flip_and_addr(
 	struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
 
 	/* program flip type */
-	REG_UPDATE(DCSURF_FLIP_CONTROL,
+	REG_SET(DCSURF_FLIP_CONTROL, 0,
 			SURFACE_FLIP_TYPE, flip_immediate);
 
 	/* HW automatically latch rest of address register on write to
@@ -258,21 +258,20 @@ static bool mem_input_program_surface_flip_and_addr(
 			break;
 
 		if (address->grph.meta_addr.quad_part != 0) {
-
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
 					address->grph.meta_addr.high_part);
 
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 					PRIMARY_META_SURFACE_ADDRESS,
 					address->grph.meta_addr.low_part);
 		}
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 				PRIMARY_SURFACE_ADDRESS_HIGH,
 				address->grph.addr.high_part);
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 				PRIMARY_SURFACE_ADDRESS,
 				address->grph.addr.low_part);
 		break;
@@ -282,40 +281,38 @@ static bool mem_input_program_surface_flip_and_addr(
 			break;
 
 		if (address->video_progressive.luma_meta_addr.quad_part != 0) {
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
+				PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
+				address->video_progressive.chroma_meta_addr.high_part);
 
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
+				PRIMARY_META_SURFACE_ADDRESS_C,
+				address->video_progressive.chroma_meta_addr.low_part);
+
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 				PRIMARY_META_SURFACE_ADDRESS_HIGH,
 				address->video_progressive.luma_meta_addr.high_part);
 
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 				PRIMARY_META_SURFACE_ADDRESS,
 				address->video_progressive.luma_meta_addr.low_part);
-
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-				PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-				address->video_progressive.chroma_meta_addr.high_part);
-
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C,
-				PRIMARY_META_SURFACE_ADDRESS_C,
-				address->video_progressive.chroma_meta_addr.low_part);
 		}
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 			PRIMARY_SURFACE_ADDRESS_HIGH_C,
 			address->video_progressive.chroma_addr.high_part);
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_C,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 			PRIMARY_SURFACE_ADDRESS_C,
 			address->video_progressive.chroma_addr.low_part);
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 			PRIMARY_SURFACE_ADDRESS_HIGH,
 			address->video_progressive.luma_addr.high_part);
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 			PRIMARY_SURFACE_ADDRESS,
 			address->video_progressive.luma_addr.low_part);
-
 		break;
 	case PLN_ADDR_TYPE_GRPH_STEREO:
 		if (address->grph_stereo.left_addr.quad_part == 0)
@@ -324,39 +321,38 @@ static bool mem_input_program_surface_flip_and_addr(
 			break;
 		if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 
-			REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH,
+			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 					SECONDARY_META_SURFACE_ADDRESS_HIGH,
 					address->grph_stereo.right_meta_addr.high_part);
 
-			REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS,
+			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 					SECONDARY_META_SURFACE_ADDRESS,
 					address->grph_stereo.right_meta_addr.low_part);
 		}
 		if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
 					address->grph_stereo.left_meta_addr.high_part);
 
-			REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 					PRIMARY_META_SURFACE_ADDRESS,
 					address->grph_stereo.left_meta_addr.low_part);
 		}
 
-		REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH,
+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 				SECONDARY_SURFACE_ADDRESS_HIGH,
 				address->grph_stereo.right_addr.high_part);
 
-		REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS,
+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 				SECONDARY_SURFACE_ADDRESS,
 				address->grph_stereo.right_addr.low_part);
 
-
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 				PRIMARY_SURFACE_ADDRESS_HIGH,
 				address->grph_stereo.left_addr.high_part);
 
-		REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 				PRIMARY_SURFACE_ADDRESS,
 				address->grph_stereo.left_addr.low_part);
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 20bd0f5..48b313b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -282,6 +282,7 @@ struct dcn_mi_registers {
 	MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
+	MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
 	MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
@@ -414,6 +415,7 @@ struct dcn_mi_registers {
 	type H_MIRROR_EN;\
 	type SURFACE_PIXEL_FORMAT;\
 	type SURFACE_FLIP_TYPE;\
+	type SURFACE_UPDATE_LOCK;\
 	type SURFACE_UPDATE_PENDING;\
 	type PRIMARY_SURFACE_ADDRESS_HIGH;\
 	type PRIMARY_SURFACE_ADDRESS;\
-- 
2.7.4