blob: d8762d859604495ce283d284213fa9b0e4630ea1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
From 67191984f4a466bd7d48410762e79aebbfc0d226 Mon Sep 17 00:00:00 2001
From: Roman Li <Roman.Li@amd.com>
Date: Fri, 24 Mar 2017 16:26:09 -0400
Subject: [PATCH 0306/4131] drm/amd/display: increase timeout for dmif dealloc
In some use-cases, e.g. multiple 4K displays,
exisitng wait time for reg update of 30msec timed out
during mode setiing that sometimes resulted in system bad state
as we continue without waiting for registry update complete.
Increasing timeout to 35msec fixes that problem.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 7acd871..884f453 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -524,7 +524,7 @@ void dce_mem_input_free_dmif(struct mem_input *mi,
REG_WAIT(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
- 10, 0xBB8);
+ 10, 3500);
if (mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
--
2.7.4
|
