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From d6599780e45df37c97ee410afb109b112a8c5ea3 Mon Sep 17 00:00:00 2001
From: Rex Zhu <Rex.Zhu@amd.com>
Date: Mon, 6 Feb 2017 12:37:44 +0800
Subject: [PATCH 0196/4131] drm/amd/display: mclk level can't be 0.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5af27aa..1ddc56c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -357,8 +357,8 @@ bool dm_pp_get_clock_levels_by_type(
* Than means the previous one is the highest
* non-boosted one. */
DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
- dc_clks->num_levels, i + 1);
- dc_clks->num_levels = i;
+ dc_clks->num_levels, i);
+ dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
@@ -366,8 +366,8 @@ bool dm_pp_get_clock_levels_by_type(
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
- dc_clks->num_levels, i + 1);
- dc_clks->num_levels = i;
+ dc_clks->num_levels, i);
+ dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
--
2.7.4
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