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From 5c057b4d466b1dc7d36c60fc19f587b7e8158fc3 Mon Sep 17 00:00:00 2001
From: Hersen Wu <hersenxs.wu@amd.com>
Date: Fri, 23 Dec 2016 15:13:13 -0500
Subject: [PATCH 0109/4131] drm/amd/display: set HBR3 and TPS4 capable flags
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 6481fb20..ea4778b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct(
&bp_cap_info))
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
bp_cap_info.DP_HBR2_CAP;
+ enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
+ bp_cap_info.DP_HBR3_EN;
+
}
+
+ /* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
+ * IS_HBR3_CAPABLE = 0.
+ */
+
/* test pattern 3 support */
enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
+ /* test pattern 4 support */
+ enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
/*
--
2.7.4
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