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From 31c74605adbf8b60f69dbba18acfec08da39d09b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 29 Apr 2016 11:20:32 -0400
Subject: [PATCH 1064/1110] drm/amdgpu/fiji: set UVD CG state when enabling UVD
DPM (v2)
Need to call the IP cg callbacks.
v2: fix gate logic
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
index e68edf0..e1b649b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
@@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
data->uvd_power_gated = bgate;
- if (bgate)
+ if (bgate) {
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
fiji_update_uvd_dpm(hwmgr, true);
- else
+ } else {
fiji_update_uvd_dpm(hwmgr, false);
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
+ }
return 0;
}
--
2.7.4
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